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2024-10-04Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell11-168/+267
2024-10-03target/i386/kvm: Report which action failed in kvm_arch_put/get_registersJulia Suvorova1-0/+23
2024-10-03kvm: Allow kvm_arch_get/put_registers to accept Error**Julia Suvorova7-14/+14
2024-10-03target/i386: Expose IBPB-BRTYPE and SBPB CPUID bits to the guestFabiano Rosas1-2/+2
2024-10-03kvm/i386: replace identity_base variable with a constantPaolo Bonzini1-18/+18
2024-10-03kvm/i386: refactor kvm_arch_init and split it into smaller functionsAni Sinha1-126/+201
2024-10-03Merge tag 'warn-pull-request' of https://gitlab.com/marcandre.lureau/qemu int...Peter Maydell1-12/+14
2024-10-02Merge tag 'pull-riscv-to-apply-20241002' of https://github.com/alistair23/qem...Peter Maydell11-17/+160
2024-10-02target/loongarch: fix -Werror=maybe-uninitialized false-positiveMarc-André Lureau1-12/+14
2024-10-02kvm/i386: fix return values of is_host_cpu_intel()Ani Sinha2-4/+4
2024-10-02kvm/i386: make kvm_filter_msr() and related definitions private to kvm moduleAni Sinha2-12/+11
2024-10-02target/i386: Raise the highest index value used for any VMCS encodingLei Wang2-1/+9
2024-10-02target/i386: Add VMX control bits for nested FRED supportXin Li (Intel)1-2/+2
2024-10-02target/i386: Delete duplicated macro definition CR4_FRED_MASKXin Li (Intel)1-6/+0
2024-10-02target/riscv/cpu_helper: Fix linking problem with semihosting disabledThomas Huth2-2/+4
2024-10-02target/riscv32: Fix masking of physical addressAndrew Jones1-3/+3
2024-10-02target: riscv: Add Svvptc extension supportAlexandre Ghiti2-0/+3
2024-10-02target/riscv: Add textra matching condition for the triggersAlvin Chang2-1/+47
2024-10-02target/riscv: Preliminary textra trigger CSR writting supportAlvin Chang2-6/+73
2024-10-02target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extensionMaria Klauchek1-0/+6
2024-10-02target/riscv: Stop timer with infinite timecmpAndrew Jones1-0/+1
2024-10-02target/riscv/kvm: Fix the group bit setting of AIAAndrew Jones1-1/+3
2024-10-02target: riscv: Enable Bit Manip for OpenTitan Ibex CPUAlistair Francis1-0/+5
2024-10-02target/riscv: fix za64rs enablingVladimir Isaev1-1/+1
2024-10-02target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied ruleDaniel Henrique Barboza1-3/+10
2024-10-02target/riscv: Add a property to set vl to ceil(AVL/2)Jason Chien3-0/+4
2024-10-01target/arm: Avoid target_ulong for physical address lookupsArd Biesheuvel2-10/+10
2024-09-28Merge tag 'pull-request-2024-09-25' of https://gitlab.com/thuth/qemu into sta...Peter Maydell6-11/+7
2024-09-27Merge tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell1-1/+1
2024-09-24target/riscv: remove break after g_assert_not_reached()Pierrick Bouvier2-3/+0
2024-09-24target/arm: remove break after g_assert_not_reached()Pierrick Bouvier1-1/+0
2024-09-24target/i386/kvm: replace assert(false) with g_assert_not_reached()Pierrick Bouvier1-2/+2
2024-09-24target/ppc: replace assert(0) with g_assert_not_reached()Pierrick Bouvier2-5/+5
2024-09-22target/ppc: Fix lxvx/stxvx facility checkFabiano Rosas1-1/+1
2024-09-20license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-laterPhilippe Mathieu-Daudé2-2/+2
2024-09-20license: Update deprecated SPDX tag LGPL-2.0+ to LGPL-2.0-or-laterPhilippe Mathieu-Daudé12-12/+12
2024-09-20target/hexagon: Rename macros.inc -> macros.h.incPhilippe Mathieu-Daudé4-4/+4
2024-09-20mark <zlib.h> with for-crc32 in a consistent mannerMichael Tokarev3-3/+3
2024-09-19target/arm: Correct ID_AA64ISAR1_EL1 value for neoverse-v1Peter Maydell1-1/+1
2024-09-19target/arm: Convert scalar [US]QSHRN, [US]QRSHRN, SQSHRUN to decodetreeRichard Henderson2-127/+63
2024-09-19target/arm: Convert vector [US]QSHRN, [US]QRSHRN, SQSHRUN to decodetreeRichard Henderson2-14/+186
2024-09-19target/arm: Convert SQSHL, UQSHL, SQSHLU (immediate) to decodetreeRichard Henderson2-131/+128
2024-09-19target/arm: Widen NeonGenNarrowEnvFn return to 64 bitsRichard Henderson5-78/+93
2024-09-19target/arm: Convert VQSHL, VQSHLU to gvecRichard Henderson6-110/+94
2024-09-19target/arm: Convert handle_scalar_simd_shli to decodetreeRichard Henderson2-35/+13
2024-09-19target/arm: Convert handle_scalar_simd_shri to decodetreeRichard Henderson2-70/+86
2024-09-19target/arm: Convert SHRN, RSHRN to decodetreeRichard Henderson2-48/+55
2024-09-19target/arm: Split out subroutines of handle_shri_with_rndaccRichard Henderson1-56/+82
2024-09-19target/arm: Push tcg_rnd into handle_shri_with_rndaccRichard Henderson1-26/+6
2024-09-19target/arm: Convert SSHLL, USHLL to decodetreeRichard Henderson2-44/+45