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2019-09-17target/riscv: Use both register name and ABI nameAtish Patra1-8/+11
2019-09-17riscv: hmp: Add a command to show virtual memory mappingsBin Meng2-0/+233
2019-09-17riscv: rv32: Root page table address can be larger than 32-bitBin Meng1-5/+5
2019-09-17target/riscv: Update the Hypervisor CSRs to v0.4Alistair Francis1-17/+18
2019-09-17target/riscv: Create function to test if FP is enabledAlistair Francis3-10/+26
2019-09-17target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace eventsPhilippe Mathieu-Daudé2-21/+16
2019-09-17target/riscv/pmp: Restrict priviledged PMP to system-mode emulationPhilippe Mathieu-Daudé2-5/+2
2019-09-17target/sparc: Switch to do_transaction_failed() hookPeter Maydell3-8/+18
2019-09-17target/sparc: Remove unused ldl_phys from dump_mmu()Peter Maydell1-3/+1
2019-09-17target/sparc: Handle bus errors in mmu_probe()Peter Maydell1-4/+25
2019-09-17target/sparc: Correctly handle bus errors in page table walksPeter Maydell1-4/+20
2019-09-17target/sparc: Check for transaction failures in MXCC stream ASI accessesPeter Maydell1-20/+37
2019-09-17target/sparc: Check for transaction failures in MMU passthrough ASIsPeter Maydell1-16/+33
2019-09-17target/sparc: Factor out the body of sparc_cpu_unassigned_access()Peter Maydell1-95/+106
2019-09-17Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-1/+3
2019-09-16hw/i386/pc: Extract e820 memory layout codePhilippe Mathieu-Daudé1-0/+1
2019-09-16Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20190915' into stagingPeter Maydell1-5/+10
2019-09-16i386/kvm: support guest access CORE cstateWanpeng Li1-1/+2
2019-09-14target/hppa: prevent trashing of temporary in do_depw_sar()Sven Schnelle1-4/+6
2019-09-14target/hppa: prevent trashing of temporary in trans_mtctl()Sven Schnelle1-1/+4
2019-09-13Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-sep-12-2019' ...Peter Maydell4-22/+15
2019-09-12target/mips: gdbstub: Revert commit 8e0b373Libo Zhou1-2/+1
2019-09-12target/mips: Switch to do_transaction_failed() hookPeter Maydell3-20/+14
2019-09-11target/xtensa: linux-user: add call0 ABI supportMax Filippov2-4/+23
2019-09-05target/arm: Inline gen_bx_im into callersRichard Henderson1-19/+7
2019-09-05target/arm: Clean up disas_thumb_insnRichard Henderson1-25/+2
2019-09-05target/arm: Convert T16, long branchesRichard Henderson2-49/+43
2019-09-05target/arm: Convert T16, Unconditional branchRichard Henderson2-7/+8
2019-09-05target/arm: Convert T16, load (literal)Richard Henderson2-40/+6
2019-09-05target/arm: Convert T16, shift immediateRichard Henderson2-24/+10
2019-09-05target/arm: Convert T16, Miscellaneous 16-bit instructionsRichard Henderson2-87/+55
2019-09-05target/arm: Convert T16, Conditional branches, Supervisor callRichard Henderson2-23/+15
2019-09-05target/arm: Convert T16, push and popRichard Henderson2-71/+22
2019-09-05target/arm: Split gen_nop_hintRichard Henderson1-43/+24
2019-09-05target/arm: Convert T16, nop hintsRichard Henderson2-2/+18
2019-09-05target/arm: Convert T16, Reverse bytesRichard Henderson2-15/+12
2019-09-05target/arm: Convert T16, Change processor stateRichard Henderson2-46/+50
2019-09-05target/arm: Convert T16, extractRichard Henderson2-13/+11
2019-09-05target/arm: Convert T16 adjust sp (immediate)Richard Henderson2-13/+11
2019-09-05target/arm: Convert T16 add, compare, move (two high registers)Richard Henderson2-47/+12
2019-09-05target/arm: Convert T16 branch and exchangeRichard Henderson2-41/+39
2019-09-05target/arm: Convert T16 one low register and immediateRichard Henderson2-42/+13
2019-09-05target/arm: Convert T16 add/sub (3 low, 2 low and imm)Richard Henderson2-24/+18
2019-09-05target/arm: Convert T16 load/store multipleRichard Henderson2-39/+17
2019-09-05target/arm: Convert T16 add pc/sp (immediate)Richard Henderson2-11/+8
2019-09-05target/arm: Convert T16 load/store (immediate offset)Richard Henderson2-89/+38
2019-09-05target/arm: Convert T16 load/store (register offset)Richard Henderson2-49/+17
2019-09-05target/arm: Convert T16 data-processing (two low regs)Richard Henderson2-145/+43
2019-09-05target/arm: Add skeleton for T16 decodetreeRichard Henderson3-0/+32
2019-09-05target/arm: Simplify disas_arm_insnRichard Henderson1-53/+16