diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2019-09-04 12:30:42 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-09-05 13:23:04 +0100 |
| commit | 6c6d237a865041972ec5b226657398f3b3018561 (patch) | |
| tree | 2a7cf5ef70e506b16266023e18ef44a58d34ca27 /target | |
| parent | c4d3095bb62bdac0b4f9cb180bd7aa0b40c2c270 (diff) | |
| download | qemu-6c6d237a865041972ec5b226657398f3b3018561.zip qemu-6c6d237a865041972ec5b226657398f3b3018561.tar.gz qemu-6c6d237a865041972ec5b226657398f3b3018561.tar.bz2 | |
target/arm: Convert T16 one low register and immediate
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-53-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/t16.decode | 11 | ||||
| -rw-r--r-- | target/arm/translate.c | 44 |
2 files changed, 13 insertions, 42 deletions
diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 2b5f368..0654275 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -133,3 +133,14 @@ SUB_rrri 0001101 ... ... ... @addsub_3 ADD_rri 0001 110 ... ... ... @addsub_2i SUB_rri 0001 111 ... ... ... @addsub_2i + +# Add, subtract, compare, move (one low register and immediate) + +%reg_8 8:3 +@arith_1i ..... rd:3 imm:8 \ + &s_rri_rot rot=0 rn=%reg_8 + +MOV_rxi 00100 ... ........ @arith_1i %s +CMP_xri 00101 ... ........ @arith_1i s=1 +ADD_rri 00110 ... ........ @arith_1i %s +SUB_rri 00111 ... ........ @arith_1i %s diff --git a/target/arm/translate.c b/target/arm/translate.c index 45d617a..4051765 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10705,48 +10705,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) store_reg(s, rd, tmp); } break; - case 2: case 3: - /* - * 0b001x_xxxx_xxxx_xxxx - * - Add, subtract, compare, move (one low register and immediate) - */ - op = (insn >> 11) & 3; - rd = (insn >> 8) & 0x7; - if (op == 0) { /* mov */ - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, insn & 0xff); - if (!s->condexec_mask) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - } else { - tmp = load_reg(s, rd); - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, insn & 0xff); - switch (op) { - case 1: /* cmp */ - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - break; - case 2: /* add */ - if (s->condexec_mask) - tcg_gen_add_i32(tmp, tmp, tmp2); - else - gen_add_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; - case 3: /* sub */ - if (s->condexec_mask) - tcg_gen_sub_i32(tmp, tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; - } - } - break; + case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ + goto illegal_op; case 4: if (insn & (1 << 11)) { rd = (insn >> 8) & 7; |