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2024-02-03include/exec: Change cpu_mmu_index argument to CPUStateRichard Henderson2-2/+2
2024-02-03include/exec: Implement cpu_mmu_index genericallyRichard Henderson1-5/+0
2024-02-03target/tricore: Populate CPUClass.mmu_indexRichard Henderson1-0/+6
2024-01-29include/qemu: Add TCGCPUOps typedef to typedefs.hRichard Henderson1-1/+1
2024-01-29target: Use vaddr in gen_intermediate_codeAnton Johansson1-1/+1
2024-01-05target/tricore: Use generic cpu_list()Gavin Shan2-26/+0
2024-01-05cpu: Call object_class_dynamic_cast() once in cpu_class_by_name()Philippe Mathieu-Daudé1-3/+1
2023-11-07hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name()Philippe Mathieu-Daudé1-2/+1
2023-11-07target: Move ArchCPUClass definition to 'cpu.h'Philippe Mathieu-Daudé2-10/+6
2023-11-07target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'Philippe Mathieu-Daudé2-2/+5
2023-11-07target: Unify QOM stylePhilippe Mathieu-Daudé2-4/+0
2023-10-22target/tricore: Use tcg_gen_*extract_tlRichard Henderson1-16/+4
2023-10-11hw/core/cpu: Return static value with gdb_arch_name()Akihiko Odaki1-2/+2
2023-10-07meson: Rename target_softmmu_arch -> target_system_archPhilippe Mathieu-Daudé1-1/+1
2023-10-04accel/tcg: Remove cpu_set_cpustate_pointersRichard Henderson1-9/+0
2023-10-04accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson1-2/+2
2023-10-03tcg: Rename cpu_env to tcg_envRichard Henderson1-113/+113
2023-10-03accel/tcg: Move CPUNegativeOffsetState into CPUStateRichard Henderson1-1/+0
2023-10-03target/*: Add instance_align to all cpu base classesRichard Henderson1-0/+1
2023-10-02Merge tag 'pull-shadow-2023-09-29' of https://repo.or.cz/qemu/armbru into sta...Stefan Hajnoczi1-3/+3
2023-09-29target/tricore: Clean up local variable shadowingPhilippe Mathieu-Daudé1-3/+3
2023-09-29target/tricore: Change effective address (ea) to target_ulongBastian Koppelmann1-8/+8
2023-09-29target/tricore: Remove CSFRs from cpu.hBastian Koppelmann1-134/+9
2023-09-28target/tricore: Fix FTOUZ being ISA v1.3.1 upBastian Koppelmann1-1/+5
2023-09-28target/tricore: Replace cpu_*_code with translator_*Bastian Koppelmann1-3/+4
2023-09-28target/tricore: Swap src and dst reg for RCRR_INSERTBastian Koppelmann1-4/+4
2023-09-28target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0Bastian Koppelmann1-2/+8
2023-09-28target/tricore: Implement hptof insnBastian Koppelmann4-0/+45
2023-09-28target/tricore: Implement ftohp insnBastian Koppelmann5-0/+48
2023-09-28target/tricore: Clarify special case for FTOUZ insnBastian Koppelmann1-0/+5
2023-09-28target/tricore: Implement FTOU insnBastian Koppelmann3-0/+36
2023-09-28target/tricore: Correctly handle FPU RM from PSWBastian Koppelmann1-2/+16
2023-09-28target/tricore: Implement CRCN insnBastian Koppelmann4-0/+73
2023-08-24target/tricore: Replace gen_cond_w with tcg_gen_negsetcond_tlRichard Henderson1-10/+6
2023-07-25target/tricore: Rename tricore_featureBastian Koppelmann4-9/+9
2023-07-25other architectures: spelling fixesMichael Tokarev3-6/+6
2023-06-26target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson1-2/+2
2023-06-21target/tricore: Fix ICR.IE offset in RESTORE insnBastian Koppelmann1-1/+3
2023-06-21target/tricore: Honour privilege changes on PSW writeBastian Koppelmann1-1/+1
2023-06-21target/tricore: Implement privilege level for all insnsBastian Koppelmann1-10/+33
2023-06-21target/tricore: Introduce priv tb flagBastian Koppelmann2-11/+20
2023-06-21target/tricore: Indirect jump insns use tcg_gen_lookup_and_goto_ptr()Bastian Koppelmann1-1/+6
2023-06-21target/tricore: ENABLE exit to main-loopBastian Koppelmann1-0/+5
2023-06-21target/tricore: Introduce DISAS_TARGET_EXITBastian Koppelmann1-13/+12
2023-06-21target/tricore: Fix RR_JLI clobbering reg A[11]Bastian Koppelmann1-1/+1
2023-06-21target/tricore: Fix helper_ret() not correctly restoring PSWBastian Koppelmann1-4/+4
2023-06-21target/tricore: Add CHECK_REG_PAIR() for insn accessing 64 bit regsBastian Koppelmann1-2/+9
2023-06-21target/tricore: Correctly fix saving PSW.CDE to CSA on callBastian Koppelmann1-1/+6
2023-06-21target/tricore: Fix out-of-bounds index in imask instructionSiqi Chen1-0/+1
2023-06-21target/tricore: Add DISABLE insn variantBastian Koppelmann2-1/+11