index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
Age
Commit message (
Expand
)
Author
Files
Lines
2024-02-13
Merge tag 'hppa64-pull-request' of https://github.com/hdeller/qemu-hppa into ...
Peter Maydell
6
-2
/
+76
2024-02-12
Merge tag 'pull-maintainer-updates-090224-1' of https://gitlab.com/stsquad/qe...
Peter Maydell
5
-0
/
+6
2024-02-11
target/hppa: PDC_BTLB_INFO uses 32-bit ints
Helge Deller
1
-1
/
+1
2024-02-11
target/hppa: Allow read-access to PSW with rsm 0,reg instruction
Helge Deller
1
-1
/
+7
2024-02-11
target/hppa: Implement do_transaction_failed handler for I/O errors
Helge Deller
3
-0
/
+25
2024-02-11
target/hppa: Add "diag 0x101" for console output support
Helge Deller
3
-0
/
+43
2024-02-09
kconfig: use "select" to enable semihosting
Paolo Bonzini
5
-0
/
+6
2024-02-09
target/riscv: add rv32i, rv32e and rv64e CPUs
Daniel Henrique Barboza
2
-0
/
+24
2024-02-09
target/riscv/cpu.c: add riscv_bare_cpu_init()
Daniel Henrique Barboza
1
-16
/
+29
2024-02-09
target/riscv: Enable xtheadsync under user mode
LIU Zhiwei
1
-10
/
+0
2024-02-09
target/riscv: support new isa extension detection devicetree properties
Conor Dooley
2
-0
/
+55
2024-02-09
target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG...
Conor Dooley
3
-2
/
+11
2024-02-09
target/riscv: Expose Zaamo and Zalrsc extensions
Rob Bradford
1
-0
/
+5
2024-02-09
target/riscv: Check 'A' and split extensions for atomic instructions
Rob Bradford
1
-22
/
+34
2024-02-09
target/riscv: Add Zaamo and Zalrsc extension infrastructure
Rob Bradford
1
-0
/
+2
2024-02-09
target/riscv: Use RISCVException as return type for all csr ops
LIU Zhiwei
1
-43
/
+74
2024-02-09
target/riscv: FCSR doesn't contain vxrm and vxsat
LIU Zhiwei
1
-8
/
+0
2024-02-09
target/riscv: Validate misa_mxl_max only once
Akihiko Odaki
2
-23
/
+21
2024-02-09
target/riscv: Move misa_mxl_max to class
Akihiko Odaki
7
-98
/
+110
2024-02-09
target/riscv: Remove misa_mxl validation
Akihiko Odaki
1
-12
/
+3
2024-02-09
target/riscv/kvm: get/set vector vregs[]
Daniel Henrique Barboza
1
-2
/
+55
2024-02-09
target/riscv/kvm: initialize 'vlenb' via get-reg-list
Daniel Henrique Barboza
1
-3
/
+82
2024-02-09
target/riscv/kvm: change kvm_reg_id to uint64_t
Daniel Henrique Barboza
1
-1
/
+1
2024-02-09
target/riscv/cpu.c: remove cpu->cfg.vlen
Daniel Henrique Barboza
3
-7
/
+6
2024-02-09
trans_rvv.c.inc: use vext_get_vlmax() in trans_vrgather_v*()
Daniel Henrique Barboza
1
-4
/
+2
2024-02-09
target/riscv: change vext_get_vlmax() arguments
Daniel Henrique Barboza
3
-14
/
+20
2024-02-09
target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax()
Daniel Henrique Barboza
1
-2
/
+9
2024-02-09
target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ()
Daniel Henrique Barboza
1
-3
/
+3
2024-02-09
target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)
Daniel Henrique Barboza
1
-2
/
+9
2024-02-09
target/riscv/vector_helper.c: use 'vlenb'
Daniel Henrique Barboza
1
-9
/
+9
2024-02-09
target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'
Daniel Henrique Barboza
1
-8
/
+8
2024-02-09
target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb'
Daniel Henrique Barboza
1
-70
/
+70
2024-02-09
target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb
Daniel Henrique Barboza
1
-6
/
+6
2024-02-09
target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'
Daniel Henrique Barboza
1
-3
/
+3
2024-02-09
target/riscv/csr.c: use 'vlenb' instead of 'vlen'
Daniel Henrique Barboza
1
-2
/
+2
2024-02-09
target/riscv: add 'vlenb' field in cpu->cfg
Daniel Henrique Barboza
2
-1
/
+4
2024-02-09
target/riscv: Implement optional CSR mcontext of debug Sdtrig extension
Alvin Chang
4
-5
/
+41
2024-02-09
target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[]
Daniel Henrique Barboza
1
-53
/
+57
2024-02-09
target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[]
Daniel Henrique Barboza
1
-32
/
+36
2024-02-09
target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[]
Daniel Henrique Barboza
1
-32
/
+37
2024-02-09
target/riscv: remove riscv_cpu_options[]
Daniel Henrique Barboza
4
-19
/
+0
2024-02-09
target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[]
Daniel Henrique Barboza
2
-29
/
+37
2024-02-09
target/riscv: move 'cbop_blocksize' to riscv_cpu_properties[]
Daniel Henrique Barboza
1
-1
/
+37
2024-02-09
target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[]
Daniel Henrique Barboza
2
-5
/
+38
2024-02-09
target/riscv: create finalize_features() for KVM
Daniel Henrique Barboza
4
-5
/
+72
2024-02-09
target/riscv: move 'elen' to riscv_cpu_properties[]
Daniel Henrique Barboza
2
-7
/
+42
2024-02-09
target/riscv: move 'vlen' to riscv_cpu_properties[]
Daniel Henrique Barboza
2
-6
/
+44
2024-02-09
target/riscv: rework 'vext_spec'
Daniel Henrique Barboza
4
-18
/
+34
2024-02-09
target/riscv: rework 'priv_spec'
Daniel Henrique Barboza
4
-31
/
+75
2024-02-09
target/riscv: move 'pmp' to riscv_cpu_properties[]
Daniel Henrique Barboza
1
-2
/
+36
[next]