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| author | Michael Tokarev <mjt@tls.msk.ru> | 2023-07-14 14:23:51 +0300 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2023-07-25 17:14:07 +0300 |
| commit | 8b81968c1cf351430dad66a1b36420f431243842 (patch) | |
| tree | 1ba710e8ade4b755d15bd89b8157c0d8cd4d9b01 /target/tricore | |
| parent | 673d8215415dc0c13e96b8d757102d942916d1b2 (diff) | |
| download | qemu-8b81968c1cf351430dad66a1b36420f431243842.zip qemu-8b81968c1cf351430dad66a1b36420f431243842.tar.gz qemu-8b81968c1cf351430dad66a1b36420f431243842.tar.bz2 | |
other architectures: spelling fixes
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/tricore')
| -rw-r--r-- | target/tricore/csfr.h.inc | 2 | ||||
| -rw-r--r-- | target/tricore/helper.c | 2 | ||||
| -rw-r--r-- | target/tricore/translate.c | 8 |
3 files changed, 6 insertions, 6 deletions
diff --git a/target/tricore/csfr.h.inc b/target/tricore/csfr.h.inc index ff004cb..cdfaf1d 100644 --- a/target/tricore/csfr.h.inc +++ b/target/tricore/csfr.h.inc @@ -1,4 +1,4 @@ -/* A(ll) access permited +/* A(ll) access permitted R(ead only) access E(nd init protected) access diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 951024d..7587c2f 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -57,7 +57,7 @@ hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } -/* TODO: Add exeption support*/ +/* TODO: Add exception support */ static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address, int rw, int tlb_error) { diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 2f32463..1947733 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -128,7 +128,7 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags) * Functions to generate micro-ops */ -/* Makros for generating helpers */ +/* Macros for generating helpers */ #define gen_helper_1arg(name, arg) do { \ TCGv_i32 helper_tmp = tcg_constant_i32(arg); \ @@ -336,8 +336,8 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) /* We generate loads and store to core special function register (csfr) through the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3 - makros R, A and E, which allow read-only, all and endinit protected access. - These makros also specify in which ISA version the csfr was introduced. */ + macros R, A and E, which allow read-only, all and endinit protected access. + These macros also specify in which ISA version the csfr was introduced. */ #define R(ADDRESS, REG, FEATURE) \ case ADDRESS: \ if (has_feature(ctx, FEATURE)) { \ @@ -362,7 +362,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset) #undef E #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg, - since no execption occurs */ + since no exception occurs */ #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ case ADDRESS: \ if (has_feature(ctx, FEATURE)) { \ |