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| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2023-06-14 12:00:39 +0200 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2023-06-21 18:09:54 +0200 |
| commit | 0b9f9b63c2d1e26cfe4e593f384898837c7c941f (patch) | |
| tree | ac81a8064c4213531f2b6b2a3498a663467fda27 /target/tricore | |
| parent | 3b5d136db6484f2b625fb98cce4fd8b7ac26e348 (diff) | |
| download | qemu-0b9f9b63c2d1e26cfe4e593f384898837c7c941f.zip qemu-0b9f9b63c2d1e26cfe4e593f384898837c7c941f.tar.gz qemu-0b9f9b63c2d1e26cfe4e593f384898837c7c941f.tar.bz2 | |
target/tricore: Add DISABLE insn variant
this variant saves the 'IE' bit to a 'd' register. The 'IE' bitfield
changed from ISA version 1.6.1, so we add icr_ie_offset to DisasContext
as with the other DISABLE insn.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230614100039.1337971-9-kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target/tricore')
| -rw-r--r-- | target/tricore/translate.c | 11 | ||||
| -rw-r--r-- | target/tricore/tricore-opcodes.h | 1 |
2 files changed, 11 insertions, 1 deletions
diff --git a/target/tricore/translate.c b/target/tricore/translate.c index f01000e..6712d98 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -75,7 +75,7 @@ typedef struct DisasContext { int mem_idx; uint32_t hflags, saved_hflags; uint64_t features; - uint32_t icr_ie_mask; + uint32_t icr_ie_mask, icr_ie_offset; } DisasContext; static int has_feature(DisasContext *ctx, int feature) @@ -7883,6 +7883,13 @@ static void decode_sys_interrupts(DisasContext *ctx) case OPC2_32_SYS_DISABLE: tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask); break; + case OPC2_32_SYS_DISABLE_D: + if (has_feature(ctx, TRICORE_FEATURE_16)) { + tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR, ctx->icr_ie_offset, 1); + tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask); + } else { + generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); + } case OPC2_32_SYS_DSYNC: break; case OPC2_32_SYS_ENABLE: @@ -8302,8 +8309,10 @@ static void tricore_tr_init_disas_context(DisasContextBase *dcbase, ctx->features = env->features; if (has_feature(ctx, TRICORE_FEATURE_161)) { ctx->icr_ie_mask = R_ICR_IE_161_MASK; + ctx->icr_ie_offset = R_ICR_IE_161_SHIFT; } else { ctx->icr_ie_mask = R_ICR_IE_13_MASK; + ctx->icr_ie_offset = R_ICR_IE_13_SHIFT; } } diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h index af63926..bc62b73 100644 --- a/target/tricore/tricore-opcodes.h +++ b/target/tricore/tricore-opcodes.h @@ -1467,6 +1467,7 @@ enum { enum { OPC2_32_SYS_DEBUG = 0x04, OPC2_32_SYS_DISABLE = 0x0d, + OPC2_32_SYS_DISABLE_D = 0x0f, /* 1.6 up */ OPC2_32_SYS_DSYNC = 0x12, OPC2_32_SYS_ENABLE = 0x0c, OPC2_32_SYS_ISYNC = 0x13, |