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2022-01-21target/riscv: rvv-1.0: Allow Zve32f extension to be turned onFrank Chang1-0/+1
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insnsFrank Chang1-0/+3
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insnsFrank Chang1-0/+18
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insnsFrank Chang1-0/+1
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for scalar fp insnsFrank Chang1-0/+21
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for configuration insnsFrank Chang1-2/+2
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang5-4/+7
2022-01-21target/riscv: rvv-1.0: Allow Zve64f extension to be turned onFrank Chang1-0/+1
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insnsFrank Chang1-3/+6
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insnsFrank Chang1-7/+25
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insnsFrank Chang1-1/+2
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for scalar fp insnsFrank Chang1-10/+31
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insnsFrank Chang1-2/+25
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insnsFrank Chang1-6/+33
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for load and store insnsFrank Chang1-4/+15
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for configuration insnsFrank Chang1-2/+4
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang5-2/+16
2022-01-21target/riscv: Support virtual time context synchronizationYifei Jiang1-0/+30
2022-01-21target/riscv: Implement virtual time adjusting with vm state changingYifei Jiang1-0/+15
2022-01-21target/riscv: Add kvm_riscv_get/put_regs_timerYifei Jiang2-0/+79
2022-01-21target/riscv: Add host cpu typeYifei Jiang2-0/+16
2022-01-21target/riscv: Handle KVM_EXIT_RISCV_SBI exitYifei Jiang2-1/+113
2022-01-21target/riscv: Support setting external interrupt by KVMYifei Jiang4-1/+28
2022-01-21target/riscv: Support start kernel directly by KVMYifei Jiang6-1/+75
2022-01-21target/riscv: Implement kvm_arch_put_registersYifei Jiang1-1/+103
2022-01-21target/riscv: Implement kvm_arch_get_registersYifei Jiang1-1/+111
2022-01-21target/riscv: Implement function kvm_arch_init_vcpuYifei Jiang1-1/+33
2022-01-21target/riscv: Add target/riscv/kvm.c to place the public kvm interfaceYifei Jiang2-0/+134
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis3-0/+8
2022-01-08target/riscv: Fixup setting GVAAlistair Francis1-15/+6
2022-01-08target/riscv: Set the opcode in DisasContextAlistair Francis1-0/+2
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot3-30/+175
2022-01-08target/riscv: modification of the trans_csrxx for 128-bit supportFrédéric Pétrot1-43/+158
2022-01-08target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot4-0/+69
2022-01-08target/riscv: adding high part of some csrsFrédéric Pétrot2-0/+6
2022-01-08target/riscv: support for 128-bit M extensionFrédéric Pétrot6-13/+295
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot5-49/+222
2022-01-08target/riscv: support for 128-bit shift instructionsFrédéric Pétrot4-44/+270
2022-01-08target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot2-4/+25
2022-01-08target/riscv: support for 128-bit bitwise instructionsFrédéric Pétrot1-2/+19
2022-01-08target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot4-10/+163
2022-01-08target/riscv: moving some insns close to similar insnsFrédéric Pétrot1-17/+17
2022-01-08target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot3-0/+26
2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot4-1/+35
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot3-9/+36
2022-01-08target/riscv: additional macros to check instruction supportFrédéric Pétrot1-4/+16
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot4-17/+17
2022-01-08target/riscv: Fix position of 'experimental' commentPhilipp Tomsich1-1/+2
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing ...Frank Chang1-8/+24
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang1-9/+25
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