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Author
Files
Lines
2022-01-21
target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
Frank Chang
1
-0
/
+1
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
Frank Chang
1
-0
/
+3
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
Frank Chang
1
-0
/
+18
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
Frank Chang
1
-0
/
+1
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
Frank Chang
1
-0
/
+21
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for configuration insns
Frank Chang
1
-2
/
+2
2022-01-21
target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
Frank Chang
5
-4
/
+7
2022-01-21
target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
Frank Chang
1
-0
/
+1
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
Frank Chang
1
-3
/
+6
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
Frank Chang
1
-7
/
+25
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
Frank Chang
1
-1
/
+2
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
Frank Chang
1
-10
/
+31
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
Frank Chang
1
-2
/
+25
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
Frank Chang
1
-6
/
+33
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for load and store insns
Frank Chang
1
-4
/
+15
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for configuration insns
Frank Chang
1
-2
/
+4
2022-01-21
target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
Frank Chang
5
-2
/
+16
2022-01-21
target/riscv: Support virtual time context synchronization
Yifei Jiang
1
-0
/
+30
2022-01-21
target/riscv: Implement virtual time adjusting with vm state changing
Yifei Jiang
1
-0
/
+15
2022-01-21
target/riscv: Add kvm_riscv_get/put_regs_timer
Yifei Jiang
2
-0
/
+79
2022-01-21
target/riscv: Add host cpu type
Yifei Jiang
2
-0
/
+16
2022-01-21
target/riscv: Handle KVM_EXIT_RISCV_SBI exit
Yifei Jiang
2
-1
/
+113
2022-01-21
target/riscv: Support setting external interrupt by KVM
Yifei Jiang
4
-1
/
+28
2022-01-21
target/riscv: Support start kernel directly by KVM
Yifei Jiang
6
-1
/
+75
2022-01-21
target/riscv: Implement kvm_arch_put_registers
Yifei Jiang
1
-1
/
+103
2022-01-21
target/riscv: Implement kvm_arch_get_registers
Yifei Jiang
1
-1
/
+111
2022-01-21
target/riscv: Implement function kvm_arch_init_vcpu
Yifei Jiang
1
-1
/
+33
2022-01-21
target/riscv: Add target/riscv/kvm.c to place the public kvm interface
Yifei Jiang
2
-0
/
+134
2022-01-08
target/riscv: Implement the stval/mtval illegal instruction
Alistair Francis
3
-0
/
+8
2022-01-08
target/riscv: Fixup setting GVA
Alistair Francis
1
-15
/
+6
2022-01-08
target/riscv: Set the opcode in DisasContext
Alistair Francis
1
-0
/
+2
2022-01-08
target/riscv: actual functions to realize crs 128-bit insns
Frédéric Pétrot
3
-30
/
+175
2022-01-08
target/riscv: modification of the trans_csrxx for 128-bit support
Frédéric Pétrot
1
-43
/
+158
2022-01-08
target/riscv: helper functions to wrap calls to 128-bit csr insns
Frédéric Pétrot
4
-0
/
+69
2022-01-08
target/riscv: adding high part of some csrs
Frédéric Pétrot
2
-0
/
+6
2022-01-08
target/riscv: support for 128-bit M extension
Frédéric Pétrot
6
-13
/
+295
2022-01-08
target/riscv: support for 128-bit arithmetic instructions
Frédéric Pétrot
5
-49
/
+222
2022-01-08
target/riscv: support for 128-bit shift instructions
Frédéric Pétrot
4
-44
/
+270
2022-01-08
target/riscv: support for 128-bit U-type instructions
Frédéric Pétrot
2
-4
/
+25
2022-01-08
target/riscv: support for 128-bit bitwise instructions
Frédéric Pétrot
1
-2
/
+19
2022-01-08
target/riscv: accessors to registers upper part and 128-bit load/store
Frédéric Pétrot
4
-10
/
+163
2022-01-08
target/riscv: moving some insns close to similar insns
Frédéric Pétrot
1
-17
/
+17
2022-01-08
target/riscv: setup everything for rv64 to support rv128 execution
Frédéric Pétrot
3
-0
/
+26
2022-01-08
target/riscv: array for the 64 upper bits of 128-bit registers
Frédéric Pétrot
4
-1
/
+35
2022-01-08
target/riscv: separation of bitwise logic and arithmetic helpers
Frédéric Pétrot
3
-9
/
+36
2022-01-08
target/riscv: additional macros to check instruction support
Frédéric Pétrot
1
-4
/
+16
2022-01-08
exec/memop: Adding signedness to quad definitions
Frédéric Pétrot
4
-17
/
+17
2022-01-08
target/riscv: Fix position of 'experimental' comment
Philipp Tomsich
1
-1
/
+2
2022-01-08
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing ...
Frank Chang
1
-8
/
+24
2022-01-08
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...
Frank Chang
1
-9
/
+25
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