diff options
| author | Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> | 2022-01-06 22:01:05 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-08 15:46:10 +1000 |
| commit | 2c64ab66c1cdb409ead121357b3e92f8f1800c03 (patch) | |
| tree | c6b8e1b6f813f37ff39c354a4111f077d3ea1e1c /target/riscv | |
| parent | b3a5d1fbebab2098d0c3cdd3732c25f5cfbe5cbc (diff) | |
| download | qemu-2c64ab66c1cdb409ead121357b3e92f8f1800c03.zip qemu-2c64ab66c1cdb409ead121357b3e92f8f1800c03.tar.gz qemu-2c64ab66c1cdb409ead121357b3e92f8f1800c03.tar.bz2 | |
target/riscv: adding high part of some csrs
Adding the high part of a very minimal set of csr.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-16-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.h | 4 | ||||
| -rw-r--r-- | target/riscv/machine.c | 2 |
2 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b9dee7d..e8c664a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -195,6 +195,10 @@ struct CPURISCVState { target_ulong hgatp; uint64_t htimedelta; + /* Upper 64-bits of 128-bit CSRs */ + uint64_t mscratchh; + uint64_t sscratchh; + /* Virtual CSRs */ /* * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 8af9caa..13b9ab3 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -179,6 +179,8 @@ static const VMStateDescription vmstate_rv128 = { .needed = rv128_needed, .fields = (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32), + VMSTATE_UINT64(env.mscratchh, RISCVCPU), + VMSTATE_UINT64(env.sscratchh, RISCVCPU), VMSTATE_END_OF_LIST() } }; |