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| author | Frank Chang <frank.chang@sifive.com> | 2022-01-18 09:45:15 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-21 15:52:56 +1000 |
| commit | da61f1256f55a5e9fc03f7c88e3caa425d6bf8cf (patch) | |
| tree | b4f55006ea147ad401779470859648a688e9a5ba /target/riscv | |
| parent | 32e579b8c510f0c8d7023d87b0cfacf782cb4a62 (diff) | |
| download | qemu-da61f1256f55a5e9fc03f7c88e3caa425d6bf8cf.zip qemu-da61f1256f55a5e9fc03f7c88e3caa425d6bf8cf.tar.gz qemu-da61f1256f55a5e9fc03f7c88e3caa425d6bf8cf.tar.bz2 | |
target/riscv: rvv-1.0: Add Zve32f support for configuration insns
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-13-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 9fa3862..fd6e74c 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -152,7 +152,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2) TCGv s1, dst; if (!require_rvv(s) || - !(has_ext(s, RVV) || s->ext_zve64f)) { + !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) { return false; } @@ -188,7 +188,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2) TCGv dst; if (!require_rvv(s) || - !(has_ext(s, RVV) || s->ext_zve64f)) { + !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) { return false; } |