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| author | Frank Chang <frank.chang@sifive.com> | 2022-01-18 09:45:19 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-21 15:52:56 +1000 |
| commit | 6db02328a7537fb62c282700f34d9b0c0a845854 (patch) | |
| tree | 05573b8f9d76581112350fe63451448f82ab0684 /target/riscv | |
| parent | f4dcf51cdcd25e8df150b0a394ccefc0611975dc (diff) | |
| download | qemu-6db02328a7537fb62c282700f34d9b0c0a845854.zip qemu-6db02328a7537fb62c282700f34d9b0c0a845854.tar.gz qemu-6db02328a7537fb62c282700f34d9b0c0a845854.tar.bz2 | |
target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-17-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index f2d3c9e..7a040b3 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2862,6 +2862,7 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a) return opfv_narrow_check(s, a) && require_rvf(s) && (s->sew != MO_64) && + require_zve32f(s) && require_zve64f(s); } @@ -2870,6 +2871,7 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) return opfv_narrow_check(s, a) && require_scale_rvf(s) && (s->sew != MO_8) && + require_scale_zve32f(s) && require_scale_zve64f(s); } @@ -2920,6 +2922,7 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) vext_check_isa_ill(s) && /* OPFV narrowing instructions ignore vs1 check */ vext_check_sd(s, a->rd, a->rs2, a->vm) && + require_scale_zve32f(s) && require_scale_zve64f(s); } |