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path: root/target/riscv/machine.c
AgeCommit message (Expand)AuthorFilesLines
2023-03-01target/riscv/cpu: remove CPUArchState::features and friendsDaniel Henrique Barboza1-3/+2
2023-03-01target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza1-2/+1
2023-03-01target/riscv: remove RISCV_FEATURE_DEBUGDaniel Henrique Barboza1-2/+1
2023-01-20hw/char: riscv_htif: Move registers from CPUArchState to HTIFStateBin Meng1-4/+2
2023-01-06target/riscv: Add itrigger_enabled field to CPURISCVStateLIU Zhiwei1-0/+15
2023-01-06target/riscv: Add smstateen supportMayuresh Chitale1-0/+21
2022-09-27target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRsFrank Chang1-15/+5
2022-09-27target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang1-1/+1
2022-09-27target/riscv: Set the CPU resetvec directlyAlistair Francis1-3/+3
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra1-0/+1
2022-09-07target/riscv: Add vstimecmp supportAtish Patra1-0/+1
2022-09-07target/riscv: Add stimecmp supportAtish Patra1-0/+1
2022-09-07hw/intc: Move mtimer/mtimecmp to aclintAtish Patra1-3/+2
2022-07-03target/riscv: Support mcycle/minstret write operationAtish Patra1-2/+23
2022-07-03target/riscv: Add support for hpmcounters/hpmeventsAtish Patra1-0/+3
2022-07-03target/riscv: Implement mcountinhibit CSRAtish Patra1-0/+1
2022-04-22target/riscv: machine: Add debug state descriptionBin Meng1-0/+32
2022-04-22target/riscv: Add *envcfg* CSRs supportAtish Patra1-0/+23
2022-02-16target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel1-0/+3
2022-02-16target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel1-0/+2
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel1-5/+5
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel1-0/+3
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel1-2/+4
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei1-2/+3
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei1-0/+1
2022-01-21target/riscv: Create xl field in envLIU Zhiwei1-0/+10
2022-01-21target/riscv: Support virtual time context synchronizationYifei Jiang1-0/+30
2022-01-08target/riscv: adding high part of some csrsFrédéric Pétrot1-0/+2
2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot1-0/+20
2021-11-17target/riscv: machine: Sort the .subsectionsBin Meng1-46/+46
2021-10-28target/riscv: Add J extension state descriptionAlexey Baturo1-0/+27
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson1-4/+6
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra1-5/+3
2020-11-03target/riscv: Add V extension state descriptionYifei Jiang1-0/+25
2020-11-03target/riscv: Add H extension state descriptionYifei Jiang1-0/+47
2020-11-03target/riscv: Add PMP state descriptionYifei Jiang1-0/+50
2020-11-03target/riscv: Add basic vmstate description of CPUYifei Jiang1-0/+74
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