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| author | Atish Patra <atish.patra@wdc.com> | 2022-06-20 16:15:56 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2022-07-03 10:03:20 +1000 |
| commit | 621f35bb2fa8babb9ab2a65033fe8d47ea5cd8ba (patch) | |
| tree | 235e0863ded9887e3c61584daf0b0344144f754b /target/riscv/machine.c | |
| parent | b1675eeb3e6e38b042a23a9647559c9c548c733d (diff) | |
| download | qemu-621f35bb2fa8babb9ab2a65033fe8d47ea5cd8ba.zip qemu-621f35bb2fa8babb9ab2a65033fe8d47ea5cd8ba.tar.gz qemu-621f35bb2fa8babb9ab2a65033fe8d47ea5cd8ba.tar.bz2 | |
target/riscv: Add support for hpmcounters/hpmevents
With SBI PMU extension, user can use any of the available hpmcounters to
track any perf events based on the value written to mhpmevent csr.
Add read/write functionality for these csrs.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-7-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/machine.c')
| -rw-r--r-- | target/riscv/machine.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 87cd55b..99193c8 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -331,6 +331,9 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINTTL(env.mcounteren, RISCVCPU), VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), + VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU, RV_MAX_MHPMCOUNTERS), + VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU, RV_MAX_MHPMCOUNTERS), + VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), |