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| author | Anup Patel <anup.patel@wdc.com> | 2022-02-04 23:16:47 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-02-16 12:24:19 +1000 |
| commit | 2b6023987955a887aae3ad6882557960b2253a4f (patch) | |
| tree | dca20684b97bdb2a8ccb8be36d814ae62152d09b /target/riscv/machine.c | |
| parent | d028ac7512f1a781a5cba7659a1d25dc972afdd4 (diff) | |
| download | qemu-2b6023987955a887aae3ad6882557960b2253a4f.zip qemu-2b6023987955a887aae3ad6882557960b2253a4f.tar.gz qemu-2b6023987955a887aae3ad6882557960b2253a4f.tar.bz2 | |
target/riscv: Implement AIA hvictl and hviprioX CSRs
The AIA hvictl and hviprioX CSRs allow hypervisor to control
interrupts visible at VS-level. This patch implements AIA hvictl
and hviprioX CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-12-anup@brainfault.org
[ Changes by AF:
- Fix possible unintilised variable error in rmw_sie()
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/machine.c')
| -rw-r--r-- | target/riscv/machine.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 65e6303..dbd7bd0 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -92,6 +92,8 @@ static const VMStateDescription vmstate_hyper = { VMSTATE_UINTTL(env.hgeie, RISCVCPU), VMSTATE_UINTTL(env.hgeip, RISCVCPU), VMSTATE_UINT64(env.htimedelta, RISCVCPU), + + VMSTATE_UINTTL(env.hvictl, RISCVCPU), VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64), VMSTATE_UINT64(env.vsstatus, RISCVCPU), |