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Author
Files
Lines
2023-02-07
target/riscv: fix ctzw behavior
Vladimir Isaev
1
-0
/
+1
2023-02-07
RISC-V: Adding XTheadFmv ISA extension
Christoph Müllner
1
-0
/
+45
2023-02-07
RISC-V: Adding T-Head FMemIdx extension
Christoph Müllner
1
-0
/
+108
2023-02-07
RISC-V: Adding T-Head MemIdx extension
Christoph Müllner
1
-0
/
+387
2023-02-07
RISC-V: Adding T-Head MemPair extension
Christoph Müllner
1
-0
/
+92
2023-02-07
RISC-V: Adding T-Head multiply-accumulate instructions
Christoph Müllner
1
-0
/
+83
2023-02-07
RISC-V: Adding XTheadCondMov ISA extension
Christoph Müllner
1
-0
/
+35
2023-02-07
RISC-V: Adding XTheadBs ISA extension
Christoph Müllner
1
-0
/
+15
2023-02-07
RISC-V: Adding XTheadBb ISA extension
Christoph Müllner
1
-0
/
+124
2023-02-07
RISC-V: Adding XTheadBa ISA extension
Christoph Müllner
1
-0
/
+39
2023-02-07
RISC-V: Adding XTheadSync ISA extension
Christoph Müllner
1
-0
/
+85
2023-02-07
RISC-V: Adding XTheadCmo ISA extension
Christoph Müllner
1
-0
/
+81
2023-02-07
target/riscv: Ensure opcode is saved for all relevant instructions
Anup Patel
7
-3
/
+21
2023-01-20
target/riscv: Introduce helper_set_rounding_mode_chkfrm
Richard Henderson
1
-20
/
+4
2023-01-06
RISC-V: Add Zawrs ISA extension support
Christoph Muellner
1
-0
/
+51
2023-01-06
target/riscv: Add itrigger support when icount is not enabled
LIU Zhiwei
3
-8
/
+8
2022-09-27
target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
Yang Liu
1
-2
/
+4
2022-09-13
target/riscv: Honour -semihosting-config userspace=on and enable=on
Peter Maydell
1
-1
/
+2
2022-09-07
target/riscv: Add Zihintpause support
Dao Lu
1
-0
/
+16
2022-09-07
target/riscv: rvv: Add mask agnostic for vector permutation instructions
Yueh-Ting (eop) Chen
1
-0
/
+1
2022-09-07
target/riscv: rvv: Add mask agnostic for vector mask instructions
Yueh-Ting (eop) Chen
1
-0
/
+3
2022-09-07
target/riscv: rvv: Add mask agnostic for vector floating-point instructions
Yueh-Ting (eop) Chen
1
-0
/
+12
2022-09-07
target/riscv: rvv: Add mask agnostic for vector integer comparison instructions
Yueh-Ting (eop) Chen
1
-0
/
+1
2022-09-07
target/riscv: rvv: Add mask agnostic for vector integer shift instructions
Yueh-Ting (eop) Chen
1
-0
/
+1
2022-09-07
target/riscv: rvv: Add mask agnostic for vx instructions
Yueh-Ting (eop) Chen
1
-0
/
+2
2022-09-07
target/riscv: rvv: Add mask agnostic for vector load / store instructions
Yueh-Ting (eop) Chen
1
-0
/
+5
2022-09-07
target/riscv: rvv: Add mask agnostic for vv instructions
Yueh-Ting (eop) Chen
1
-0
/
+3
2022-07-03
target/riscv: Minimize the calls to decode_save_opc
Richard Henderson
3
-0
/
+8
2022-07-03
target/riscv: Remove condition guarding register zero for auipc and lui
Víctor Colombo
1
-6
/
+2
2022-06-10
target/riscv: trans_rvv: Avoid assert for RV32 and e64
Alistair Francis
1
-2
/
+10
2022-06-10
target/riscv: rvv: Add tail agnostic for vector permutation instructions
eopXD
1
-2
/
+5
2022-06-10
target/riscv: rvv: Add tail agnostic for vector mask instructions
eopXD
1
-0
/
+6
2022-06-10
target/riscv: rvv: Add tail agnostic for vector floating-point instructions
eopXD
1
-0
/
+17
2022-06-10
target/riscv: rvv: Add tail agnostic for vector integer merge and move instru...
eopXD
1
-4
/
+8
2022-06-10
target/riscv: rvv: Add tail agnostic for vector integer shift instructions
eopXD
1
-1
/
+2
2022-06-10
target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
eopXD
1
-2
/
+11
2022-06-10
target/riscv: rvv: Add tail agnostic for vector load / store instructions
eopXD
1
-0
/
+6
2022-06-10
target/riscv: rvv: Add tail agnostic for vv instructions
eopXD
1
-1
/
+2
2022-06-10
target/riscv: rvv: Early exit when vstart >= vl
eopXD
1
-0
/
+27
2022-06-10
target/riscv: add support for zmmul extension v0.1
Weiwei Li
1
-6
/
+12
2022-05-24
target/riscv: rvv: Fix early exit condition for whole register load/store
eopXD
1
-27
/
+31
2022-04-29
target/riscv: rvk: add support for zksed/zksh extension
Weiwei Li
1
-0
/
+58
2022-04-29
target/riscv: rvk: add support for sha512 related instructions for RV64 in zk...
Weiwei Li
1
-0
/
+53
2022-04-29
target/riscv: rvk: add support for sha512 related instructions for RV32 in zk...
Weiwei Li
1
-0
/
+100
2022-04-29
target/riscv: rvk: add support for sha256 related instructions in zknh extension
Weiwei Li
1
-0
/
+55
2022-04-29
target/riscv: rvk: add support for zkne/zknd extension in RV64
Weiwei Li
1
-0
/
+54
2022-04-29
target/riscv: rvk: add support for zknd/zkne extension in RV32
Weiwei Li
1
-0
/
+71
2022-04-29
target/riscv: rvk: add support for zbkx extension
Weiwei Li
1
-0
/
+18
2022-04-29
target/riscv: rvk: add support for zbkc extension
Weiwei Li
1
-2
/
+2
2022-04-29
target/riscv: rvk: add support for zbkb extension
Weiwei Li
1
-12
/
+82
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