aboutsummaryrefslogtreecommitdiff
path: root/target/riscv
AgeCommit message (Expand)AuthorFilesLines
2023-02-27target/riscv/cpu: Move Floating-Point fields closerPhilippe Mathieu-Daudé1-3/+3
2023-02-27target/cpu: Restrict do_transaction_failed() handlers to sysemuPhilippe Mathieu-Daudé1-5/+5
2023-02-27target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemuPhilippe Mathieu-Daudé1-1/+1
2023-02-23target/riscv: Fix vslide1up.vf and vslide1down.vfLIU Zhiwei1-2/+2
2023-02-23target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()Daniel Henrique Barboza1-1/+1
2023-02-23target/riscv: Smepmp: Skip applying default rules when address matchesHimanshu Chauhan1-3/+6
2023-02-23target/riscv: Remove privileged spec version restriction for RVVFrank Chang2-15/+8
2023-02-08riscv: Clean up includesMarkus Armbruster1-1/+0
2023-02-07target/riscv: fix SBI getchar handler for KVMVladimir Isaev1-2/+3
2023-02-07target/riscv: fix ctzw behaviorVladimir Isaev1-0/+1
2023-02-07target/riscv: fix for virtual instr exceptionDeepak Gupta1-0/+1
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner5-3/+55
2023-02-07RISC-V: Add initial support for T-Head C906Christoph Müllner3-0/+38
2023-02-07RISC-V: Set minimum priv version for Zfh to 1.11Christoph Müllner1-1/+1
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner5-1/+123
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner5-1/+464
2023-02-07RISC-V: Adding T-Head MemPair extensionChristoph Müllner5-1/+109
2023-02-07RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner5-1/+96
2023-02-07RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner5-1/+43
2023-02-07RISC-V: Adding XTheadBs ISA extensionChristoph Müllner5-1/+23
2023-02-07RISC-V: Adding XTheadBb ISA extensionChristoph Müllner5-2/+149
2023-02-07RISC-V: Adding XTheadBa ISA extensionChristoph Müllner5-1/+66
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner7-1/+105
2023-02-07RISC-V: Adding XTheadCmo ISA extensionChristoph Müllner6-0/+131
2023-02-07target/riscv: set tval for triggered watchpointsSergey Matyukevich2-1/+6
2023-02-07target/riscv: Ensure opcode is saved for all relevant instructionsAnup Patel7-3/+21
2023-02-07target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAXAnup Patel1-0/+24
2023-02-07target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIPAnup Patel2-6/+8
2023-02-07target/riscv: Update VS timer whenever htimedelta changesAnup Patel1-0/+16
2023-01-20target/riscv: Remove helper_set_rod_rounding_modeRichard Henderson3-10/+0
2023-01-20target/riscv: Introduce helper_set_rounding_mode_chkfrmRichard Henderson4-20/+61
2023-01-20target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1Andrew Bresticker1-0/+6
2023-01-20target/riscv: Fix up masking of vsip/vsie accessesAndrew Bresticker1-24/+11
2023-01-20target/riscv: Use TARGET_FMT_lx for env->mhartidBin Meng1-3/+3
2023-01-20target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()Daniel Henrique Barboza1-194/+205
2023-01-20target/riscv/cpu: set cpu->cfg in register_cpu_props()Daniel Henrique Barboza2-0/+44
2023-01-20target/riscv/cpu.c: Fix elen checkDongxue Zhang1-1/+1
2023-01-20hw/char: riscv_htif: Move registers from CPUArchState to HTIFStateBin Meng2-8/+2
2023-01-18bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé2-6/+6
2023-01-06Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qem...Peter Maydell18-108/+874
2023-01-06RISC-V: Add Zawrs ISA extension supportChristoph Muellner5-0/+64
2023-01-06target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+Bin Meng1-0/+6
2023-01-06target/riscv: Simplify helper_sret() a little bitBin Meng1-14/+6
2023-01-06target/riscv: Set pc_succ_insn for !rvc illegal insnRichard Henderson1-8/+4
2023-01-06target/riscv: Fix mret exception cause when no pmp rule is configuredBin Meng1-1/+1
2023-01-06target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()Bin Meng1-0/+4
2023-01-06target/riscv: support cache-related PMU events in virtual modeJim Shu1-1/+1
2023-01-06target/riscv: Typo fix in sstc() predicateAnup Patel1-1/+1
2023-01-06target/riscv: Add itrigger_enabled field to CPURISCVStateLIU Zhiwei4-2/+20
2023-01-06target/riscv: Enable native debug itriggerLIU Zhiwei1-0/+72
generated by cgit v1.1 at 2025-01-06 22:55:06 +0000