riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
12 days	target/riscv: Add check for 16-bit aligned PC for different priv versions.	Yu-Ming Chang	1	-2/+6
12 days	target/riscv: fixes a bug against `ssamoswap` behavior in M-mode	Deepak Gupta	1	-0/+17
2025-03-04	target/riscv: Add CTR sctrclr instruction.	Rajnesh Kanwal	1	-0/+11
2025-03-04	target/riscv: Add support to record CTR entries.	Rajnesh Kanwal	3	-0/+98
2025-03-04	target/riscv: Remove obsolete sfence.vm instruction	Rajnesh Kanwal	1	-5/+0
2025-01-19	target/riscv: Add Smrnmi mnret instruction	Tommy Wu	1	-0/+20
2024-11-07	target/riscv: Set vdata.vm field for vector load/store whole register instruc...	Max Chou	1	-0/+3
2024-10-30	target/riscv: implement zicfiss instructions	Deepak Gupta	1	-0/+114
2024-10-30	target/riscv: update `decode_save_opc` to store extra word2	Deepak Gupta	10	-29/+29
2024-10-30	target/riscv: zicfilp `lpad` impl and branch tracking	Deepak Gupta	1	-0/+55
2024-09-24	target/riscv: remove break after g_assert_not_reached()	Pierrick Bouvier	1	-2/+0
2024-08-06	target/riscv: Relax fld alignment requirement	LIU Zhiwei	1	-4/+14
2024-08-06	target/riscv: Add MXLEN check for F/D/Q applies to zama16b	LIU Zhiwei	1	-2/+6
2024-08-06	target/riscv: Remove redundant insn length check for zama16b	LIU Zhiwei	3	-6/+6
2024-07-18	target/riscv: Add amocas.[b\|h] for Zabha	LIU Zhiwei	1	-0/+14
2024-07-18	target/riscv: Move gen_cmpxchg before adding amocas.[b\|h]	LIU Zhiwei	1	-13/+0
2024-07-18	target/riscv: Add AMO instructions for Zabha	LIU Zhiwei	1	-0/+131
2024-07-18	target/riscv: Move gen_amo before implement Zabha	LIU Zhiwei	1	-21/+0
2024-07-18	target/riscv: Support Zama16b extension	LIU Zhiwei	4	-22/+54
2024-07-18	target/riscv: Add zcmop extension	LIU Zhiwei	1	-0/+29
2024-07-18	target/riscv: Add zimop extension	LIU Zhiwei	1	-0/+37
2024-06-03	target/riscv: rvzicbo: Fixup CBO extension register calculation	Alistair Francis	1	-4/+12
2024-06-03	target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen in...	Max Chou	1	-12/+4
2024-06-03	target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w	Max Chou	1	-0/+1
2024-06-03	target/riscv: rvv: Check single width operator for vector fp widen instructions	Max Chou	1	-0/+5
2024-06-03	target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w ins...	Max Chou	1	-2/+18
2024-06-03	target/riscv: Add support for Zve32x extension	Jason Chien	1	-2/+2
2024-06-03	trans_privileged.c.inc: set (m\|s)tval on ebreak breakpoint	Daniel Henrique Barboza	1	-0/+2
2024-06-03	target/riscv: Raise exceptions on wrs.nto	Andrew Jones	1	-9/+20
2024-03-22	target/riscv: enable 'vstart_eq_zero' in the end of insns	Ivan Klokov	3	-48/+53
2024-03-22	trans_rvv.c.inc: remove redundant mark_vs_dirty() calls	Daniel Henrique Barboza	1	-8/+3
2024-03-22	target/riscv: remove 'over' brconds from vector trans	Daniel Henrique Barboza	3	-129/+0
2024-03-22	target/riscv: always clear vstart for ldst_whole insns	Daniel Henrique Barboza	1	-29/+23
2024-03-22	target/riscv: always clear vstart in whole vec move insns	Daniel Henrique Barboza	1	-3/+0
2024-03-22	trans_rvv.c.inc: set vstart = 0 in int scalar move insns	Daniel Henrique Barboza	1	-2/+8
2024-03-08	trans_rvv.c.inc: remove 'is_store' bool from load/store fns	Daniel Henrique Barboza	1	-29/+29
2024-03-08	trans_rvv.c.inc: mark_vs_dirty() before loads and stores	Daniel Henrique Barboza	1	-15/+8
2024-03-08	RISC-V: Add support for Ztso	Palmer Dabbelt	3	-5/+42
2024-03-08	target/riscv: Update $ra with current $pc in trans_cm_jalt()	Jason Chien	1	-1/+5
2024-02-09	target/riscv: Enable xtheadsync under user mode	LIU Zhiwei	1	-10/+0
2024-02-09	target/riscv: Check 'A' and split extensions for atomic instructions	Rob Bradford	1	-22/+34
2024-02-09	trans_rvv.c.inc: use vext_get_vlmax() in trans_vrgather_v*()	Daniel Henrique Barboza	1	-4/+2
2024-02-09	target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ()	Daniel Henrique Barboza	1	-3/+3
2024-02-09	target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'	Daniel Henrique Barboza	1	-8/+8
2024-02-09	target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb'	Daniel Henrique Barboza	1	-70/+70
2024-02-09	target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb	Daniel Henrique Barboza	1	-6/+6
2024-02-09	target/riscv: Check for 'A' extension on all atomic instructions	Rob Bradford	1	-0/+11
2024-01-10	target/riscv: Add support for Zacas extension	Weiwei Li	1	-0/+150
2024-01-10	target/riscv: Fix th.dcache.cval1 priviledge check	LIU Zhiwei	1	-1/+1
2024-01-10	target/riscv: The whole vector register move instructions depend on vsew	Max Chou	1	-2/+1