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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-01-31 21:20:02 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-02-07 08:19:23 +1000 |
| commit | c9410a689f9f8c79378bd6d806bac3495b1eb856 (patch) | |
| tree | ec29d4b7c5aee05aa51483b35da9d34dc7b29239 /target/riscv/insn_trans | |
| parent | 134c3ffa34d005861f37cf6258b09df229e7be22 (diff) | |
| download | qemu-c9410a689f9f8c79378bd6d806bac3495b1eb856.zip qemu-c9410a689f9f8c79378bd6d806bac3495b1eb856.tar.gz qemu-c9410a689f9f8c79378bd6d806bac3495b1eb856.tar.bz2 | |
RISC-V: Adding XTheadBa ISA extension
This patch adds support for the XTheadBa ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-4-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn_trans')
| -rw-r--r-- | target/riscv/insn_trans/trans_xthead.c.inc | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index f35bf6e..a6fb813 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -16,6 +16,12 @@ * this program. If not, see <http://www.gnu.org/licenses/>. */ +#define REQUIRE_XTHEADBA(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadba) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADCMO(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadcmo) { \ return false; \ @@ -28,6 +34,39 @@ } \ } while (0) +/* XTheadBa */ + +/* + * th.addsl is similar to sh[123]add (from Zba), but not an + * alternative encoding: while sh[123] applies the shift to rs1, + * th.addsl shifts rs2. + */ + +#define GEN_TH_ADDSL(SHAMT) \ +static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TCGv arg2) \ +{ \ + TCGv t = tcg_temp_new(); \ + tcg_gen_shli_tl(t, arg2, SHAMT); \ + tcg_gen_add_tl(ret, t, arg1); \ + tcg_temp_free(t); \ +} + +GEN_TH_ADDSL(1) +GEN_TH_ADDSL(2) +GEN_TH_ADDSL(3) + +#define GEN_TRANS_TH_ADDSL(SHAMT) \ +static bool trans_th_addsl##SHAMT(DisasContext *ctx, \ + arg_th_addsl##SHAMT * a) \ +{ \ + REQUIRE_XTHEADBA(ctx); \ + return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL); \ +} + +GEN_TRANS_TH_ADDSL(1) +GEN_TRANS_TH_ADDSL(2) +GEN_TRANS_TH_ADDSL(3) + /* XTheadCmo */ static inline int priv_level(DisasContext *ctx) |