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AgeCommit message (Expand)AuthorFilesLines
2023-06-13target/riscv: Enable PC-relative translationWeiwei Li2-3/+13
2023-06-13target/riscv: Use true diff for gen_pc_plus_diffWeiwei Li2-5/+3
2023-06-13target/riscv: Change gen_set_pc_imm to gen_update_pcWeiwei Li5-8/+8
2023-06-13target/riscv: Change gen_goto_tb to work on displacementsWeiwei Li1-2/+2
2023-06-13target/riscv: Fix target address to update badaddrWeiwei Li2-9/+18
2023-06-13target/riscv: Reuse tb->flags.FSMayuresh Chitale1-3/+4
2023-06-13target/riscv: Update check for Zca/Zcf/ZcdWeiwei Li3-13/+18
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson2-24/+8
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson1-78/+51
2023-05-05target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu1-2/+2
2023-05-05target/riscv: Separate priv from mmu_idxFei Wu2-14/+2
2023-05-05target/riscv: Add a tb flags field for vstartLIU Zhiwei1-7/+7
2023-05-05target/riscv: Encode the FS and VS on a normal way for tb flagsLIU Zhiwei2-5/+5
2023-05-05target/riscv: remove cpu->cfg.ext_eDaniel Henrique Barboza1-1/+1
2023-05-05target/riscv: Fix format for commentsWeiwei Li1-3/+5
2023-05-05target/riscv: Fix format for indentationWeiwei Li1-14/+14
2023-05-05target/riscv: Set opcode to env->bins for illegal/virtual instruction faultWeiwei Li1-0/+2
2023-05-05target/riscv: Fix itrigger when icount is usedLIU Zhiwei1-0/+6
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li1-1/+27
2023-05-05target/riscv: add support for Zcmp extensionWeiwei Li1-1/+186
2023-05-05target/riscv: add support for Zcb extensionWeiwei Li1-0/+100
2023-05-05target/riscv: add support for Zcd extensionWeiwei Li1-0/+18
2023-05-05target/riscv: add support for Zcf extensionWeiwei Li1-0/+18
2023-05-05target/riscv: add support for Zca extensionWeiwei Li1-2/+2
2023-05-05target/riscv: redirect XVentanaCondOps to use the Zicond functionsPhilipp Tomsich1-15/+3
2023-05-05target/riscv: refactor Zicond supportPhilipp Tomsich1-15/+21
2023-03-07Merge tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt...Peter Maydell1-0/+57
2023-03-05target/riscv: Avoid tcg_const_*Richard Henderson2-3/+3
2023-03-05target/riscv: Drop tcg_temp_freeRichard Henderson9-208/+1
2023-03-05target/riscv: Drop temp_newRichard Henderson1-1/+1
2023-03-05target/riscv: implement Zicbom extensionChristoph Muellner1-0/+27
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner1-0/+30
2023-03-01target/riscv: Add support for Zicond extensionWeiwei Li1-0/+49
2023-03-01RISC-V: XTheadMemPair: Remove register restrictions for store-pairChristoph Müllner1-4/+0
2023-03-01target/riscv: Simplify check for EEW = 64 in trans_rvv.c.incWeiwei Li1-8/+4
2023-03-01target/riscv: Fix check for vector load/store instructions when EEW=64Weiwei Li1-5/+4
2023-03-01target/riscv: Add support for Zvfh/zvfhmin extensionsWeiwei Li1-2/+29
2023-03-01target/riscv: Remove redundunt check for zve32f and zve64fWeiwei Li1-107/+21
2023-03-01target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.incWeiwei Li1-4/+4
2023-03-01target/riscv: Simplify check for Zve32f and Zve64fWeiwei Li1-6/+2
2023-03-01target/riscv: Simplify the check for Zfhmin and ZhinxminWeiwei Li1-13/+12
2023-02-07target/riscv: fix ctzw behaviorVladimir Isaev1-0/+1
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner1-0/+45
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner1-0/+108
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner1-0/+387
2023-02-07RISC-V: Adding T-Head MemPair extensionChristoph Müllner1-0/+92
2023-02-07RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner1-0/+83
2023-02-07RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner1-0/+35
2023-02-07RISC-V: Adding XTheadBs ISA extensionChristoph Müllner1-0/+15
2023-02-07RISC-V: Adding XTheadBb ISA extensionChristoph Müllner1-0/+124
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