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2023-06-13target/riscv: Smepmp: Return error when access permission not allowed in PMPHimanshu Chauhan1-8/+2
2023-06-13target/riscv/vector_helper.c: Remove the check for extra tail elementsXiao Wang1-16/+6
2023-06-13target/riscv/vector_helper.c: clean up reference of MTYPEXiao Wang1-5/+1
2023-06-13target/riscv: Fix initialized value for cur_pmmaskWeiwei Li1-2/+2
2023-06-13target/riscv: Remove pc_succ_insn from DisasContextWeiwei Li1-6/+1
2023-06-13target/riscv: Enable PC-relative translationWeiwei Li4-20/+74
2023-06-13target/riscv: Use true diff for gen_pc_plus_diffWeiwei Li3-12/+9
2023-06-13target/riscv: Change gen_set_pc_imm to gen_update_pcWeiwei Li6-13/+13
2023-06-13target/riscv: Change gen_goto_tb to work on displacementsWeiwei Li2-5/+7
2023-06-13target/riscv: Introduce cur_insn_len into DisasContextWeiwei Li1-1/+3
2023-06-13target/riscv: Fix target address to update badaddrWeiwei Li3-20/+28
2023-06-13target/riscv: Pass RISCVCPUConfig as target_info to disassemble_infoWeiwei Li1-0/+1
2023-06-13target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.hWeiwei Li2-113/+137
2023-06-13target/riscv: smstateen knobsMayuresh Chitale1-1/+2
2023-06-13target/riscv: Reuse tb->flags.FSMayuresh Chitale2-3/+10
2023-06-13target/riscv: smstateen check for fcsrMayuresh Chitale1-0/+15
2023-06-13target/riscv: Update cur_pmmask/base when xl changesWeiwei Li1-1/+8
2023-06-13target/riscv: Fix pointer mask transformation for vector addressWeiwei Li1-1/+1
2023-06-13target/riscv: Deny access if access is partially inside the PMP entryWeiwei Li1-2/+2
2023-06-13target/riscv: Separate pmp_update_rule() in pmpcfg_csr_writeWeiwei Li1-14/+2
2023-06-13target/riscv: Flush TLB only when pmpcfg/pmpaddr really changesWeiwei Li1-10/+18
2023-06-13target/riscv: Flush TLB when pmpaddr is updatedWeiwei Li1-0/+1
2023-06-13target/riscv: Update the next rule addr in pmpaddr_csr_write()Weiwei Li1-3/+7
2023-06-13target/riscv: Flush TLB when MMWP or MML bits are changedWeiwei Li1-0/+3
2023-06-13target/riscv: Remove unused paramters in pmp_hart_has_privs_default()Weiwei Li1-6/+3
2023-06-13target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabledWeiwei Li1-24/+26
2023-06-13target/riscv: Change the return type of pmp_hart_has_privs() to boolWeiwei Li3-27/+21
2023-06-13target/riscv: Make the short cut really work in pmp_hart_has_privsWeiwei Li1-0/+1
2023-06-13target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmpWeiwei Li1-10/+6
2023-06-13target/riscv: Update pmp_get_tlb_size()Weiwei Li3-22/+57
2023-06-13target/riscv: rework write_misa()Daniel Henrique Barboza3-29/+27
2023-06-13target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()Daniel Henrique Barboza1-12/+47
2023-06-13target/riscv/cpu.c: validate extensions before riscv_timer_init()Daniel Henrique Barboza1-7/+4
2023-06-13target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()Daniel Henrique Barboza1-17/+33
2023-06-13target/riscv/cpu.c: add priv_spec validate/disable_exts helpersDaniel Henrique Barboza1-35/+56
2023-06-13target/riscv: Update check for Zca/Zcf/ZcdWeiwei Li4-15/+21
2023-06-13target/riscv: Mask the implicitly enabled extensions in isa_string based on p...Weiwei Li1-1/+2
2023-06-13target/riscv: add PRIV_VERSION_LATESTDaniel Henrique Barboza2-4/+6
2023-06-13target/riscv/cpu.c: remove set_priv_version()Daniel Henrique Barboza1-17/+12
2023-06-13target/riscv/cpu.c: remove set_vext_version()Daniel Henrique Barboza1-6/+1
2023-06-13target/riscv/cpu.c: add riscv_cpu_validate_v()Daniel Henrique Barboza1-41/+48
2023-06-13target/riscv: Move zc* out of the experimental propertiesWeiwei Li1-8/+8
2023-06-13target/riscv/vector_helper.c: skip set tail when vta is zeroDaniel Henrique Barboza1-3/+8
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson3-26/+8
2023-06-05tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson1-0/+4
2023-06-05tcg: Split out tcg/oversized-guest.hRichard Henderson1-0/+1
2023-05-05target/riscv: add Ventana's Veyron V1 CPURahul Pathak3-0/+43
2023-05-05riscv: Make sure an exception is raised if a pte is malformedAlexandre Ghiti2-4/+12
2023-05-05target/riscv: Fix Guest Physical Address TranslationIrina Ryapolova1-9/+16
2023-05-05target/riscv: Restore the predicate() NULL check behaviorBin Meng1-2/+9
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