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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-03-30 11:46:36 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | 22c2f87ab2e5c2a57e4a2ab2a02e89fe4dad608a (patch) | |
| tree | 2b05482abc46d398599705459b4108f64aeca706 /target/riscv/insn_trans | |
| parent | 77dff6509c5655fe959acf7a6d4fe923b6f292b8 (diff) | |
| download | qemu-22c2f87ab2e5c2a57e4a2ab2a02e89fe4dad608a.zip qemu-22c2f87ab2e5c2a57e4a2ab2a02e89fe4dad608a.tar.gz qemu-22c2f87ab2e5c2a57e4a2ab2a02e89fe4dad608a.tar.bz2 | |
target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
decode_save_opc() will not work for generate_exception(), since 0 is passed
to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
not be restored in this case.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230330034636.44585-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn_trans')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvh.c.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc index 9248b48..4b730cd 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -20,6 +20,8 @@ static bool check_access(DisasContext *ctx) { if (!ctx->hlsx) { + tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, + offsetof(CPURISCVState, bins)); if (ctx->virt_enabled) { generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); } else { |