aboutsummaryrefslogtreecommitdiff
path: root/target/riscv/csr.c
AgeCommit message (Expand)AuthorFilesLines
2024-01-10target/riscv: Assert that the CSR numbers will be correctAlistair Francis1-1/+4
2024-01-10target/riscv: Not allow write mstatus_vs without RVVLIU Zhiwei1-1/+4
2024-01-05target/riscv: Fix mcycle/minstret increment behaviorXu Lu1-7/+7
2023-11-07target/riscv: Don't assume PMU counters are continuousRob Bradford1-2/+3
2023-11-07target/riscv: correct csr_ops[CSR_MSECCFG]Heinrich Schuchardt1-2/+5
2023-11-07target/riscv: add zicntr extension flag for TCGDaniel Henrique Barboza1-0/+4
2023-11-07Add epmp to extensions list and rename it to smepmpHimanshu Chauhan1-3/+3
2023-11-07target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal1-18/+178
2023-11-07target/riscv: Add M-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal1-28/+251
2023-11-07target/riscv: Without H-mode mask all HS mode inturrupts in mie.Rajnesh Kanwal1-1/+1
2023-11-07target/riscv: rename ext_icsr to ext_zicsrDaniel Henrique Barboza1-1/+1
2023-10-12target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.cDaniel Henrique Barboza1-0/+1
2023-09-11target/riscv: don't read CSR in riscv_csrrw_do64Nikita Shubin1-9/+15
2023-09-11target/riscv: Align the AIA model to v1.0 ratified specTommy Wu1-2/+5
2023-09-11target/riscv: Update CSR bits name for svadu extensionWeiwei Li1-6/+6
2023-09-11target/riscv: Implement WARL behaviour for mcountinhibit/mcounterenRob Bradford1-2/+9
2023-09-08riscv: spelling fixesMichael Tokarev1-2/+2
2023-08-31target/helpers: Remove unnecessary 'qemu/main-loop.h' headerPhilippe Mathieu-Daudé1-1/+0
2023-07-10target/riscv: update cur_pmbase/pmmask based on mode affected by MPRVWeiwei Li1-7/+20
2023-07-10target/riscv: Remove redundant assignment to SXLWeiwei Li1-4/+0
2023-07-10target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabledWeiwei Li1-6/+4
2023-06-13target/riscv: smstateen check for fcsrMayuresh Chitale1-0/+15
2023-06-13target/riscv: Update cur_pmmask/base when xl changesWeiwei Li1-1/+8
2023-06-13target/riscv: rework write_misa()Daniel Henrique Barboza1-27/+24
2023-05-05target/riscv: Restore the predicate() NULL check behaviorBin Meng1-2/+9
2023-05-05target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_indexRichard Henderson1-5/+1
2023-05-05target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu1-2/+1
2023-05-05target/riscv: Add a general status enum for extensionsLIU Zhiwei1-7/+7
2023-05-05target/riscv: fix H extension TVM trapYi Chen1-21/+35
2023-05-05target/riscv: Legalize MPP value in write_mstatusWeiwei Li1-0/+32
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li1-17/+21
2023-05-05target/riscv: Fix format for commentsWeiwei Li1-3/+3
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li1-23/+23
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li1-2/+34
2023-05-05target/riscv: Simplify arguments for riscv_csrrw_checkWeiwei Li1-8/+4
2023-05-05target/riscv: Simplify type conversion for CPURISCVStateWeiwei Li1-24/+11
2023-05-05target/riscv: Avoid env_archcpu() when reading RISCVCPUConfigWeiwei Li1-28/+12
2023-03-07includes: move tb_flush into its own headerAlex Bennée1-0/+1
2023-03-06riscv: Allow user to set the satp modeAlexandre Ghiti1-7/+5
2023-03-06riscv: Change type of valid_vm_1_10_[32|64] to boolAlexandre Ghiti1-10/+11
2023-03-01Merge patch series "RISCVCPUConfig related cleanups"Palmer Dabbelt1-61/+48
2023-03-01target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfigDaniel Henrique Barboza1-23/+9
2023-03-01target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointersDaniel Henrique Barboza1-38/+12
2023-03-01target/riscv/csr.c: simplify mctr()Daniel Henrique Barboza1-3/+2
2023-03-01target/riscv/csr.c: use env_archcpu() in ctr()Daniel Henrique Barboza1-2/+1
2023-03-01Merge patch series "target/riscv: Add support for Svadu extension"Palmer Dabbelt1-6/+20
2023-03-01target/riscv: Add csr support for svaduWeiwei Li1-6/+11
2023-03-01target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and h...Weiwei Li1-4/+9
2023-03-01target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc...Weiwei Li1-2/+6
2023-03-01Merge patch series "target/riscv: Various fixes to gdbstub and CSR access"Palmer Dabbelt1-160/+181
generated by cgit v1.1 at 2024-08-24 10:39:47 +0000