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path: root/target/riscv/csr.c
AgeCommit message (Expand)AuthorFilesLines
4 daystarget/riscv: introduce ssp and enabling controls for zicfissDeepak Gupta1-0/+52
4 daystarget/riscv: additional code information for sw checkDeepak Gupta1-0/+1
4 daystarget/riscv: Introduce elp state and enabling controls for zicfilpDeepak Gupta1-0/+31
4 daystarget/riscv/csr.c: Fix an access to VXSATEvgenii Prokopiev1-2/+2
2024-07-18target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSRYu-Ming Chang1-5/+52
2024-07-18target/riscv: More accurately model priv mode filtering.Rajnesh Kanwal1-1/+4
2024-07-18target/riscv: Start counters from both mhpmcounter and mcountinhibitRajnesh Kanwal1-22/+53
2024-07-18target/riscv: Enforce WARL behavior for scounteren/hcounterenAtish Patra1-2/+10
2024-07-18target/riscv: Save counter values during countinhibit updateAtish Patra1-12/+22
2024-07-18target/riscv: Implement privilege mode filtering for cycle/instretAtish Patra1-35/+82
2024-07-18target/riscv: Only set INH fields if priv mode is availableAtish Patra1-4/+25
2024-07-18target/riscv: Add cycle & instret privilege mode filtering supportKaiwen Xue1-1/+137
2024-07-18target/riscv: Fix the predicate functions for mhpmeventhX CSRsAtish Patra1-29/+38
2024-07-18target/riscv: Validate the mode in write_vstvecJiayi Li1-1/+6
2024-06-26target/riscv: fix instructions count handling in icount modeClément Léger1-13/+17
2024-06-26target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32Fea.Wang1-0/+31
2024-06-26target/riscv: Add 'P1P13' bit in SMSTATEEN0Fea.Wang1-0/+8
2024-06-26target/riscv: Move Guest irqs out of the core local irqs range.Rajnesh Kanwal1-1/+8
2024-06-26target/riscv: Extend virtual irq csrs masks to be 64 bit wide.Rajnesh Kanwal1-7/+7
2024-06-03target/riscv: Add support for Zve32x extensionJason Chien1-1/+1
2024-06-03target/riscv/kvm: Fix exposure of ZkrAndrew Jones1-4/+14
2024-03-08target/riscv: UPDATE xATP write CSRIrina Ryapolova1-23/+29
2024-03-08target/riscv: FIX xATP_MODE validationIrina Ryapolova1-2/+2
2024-03-08target/riscv: Reset henvcfg to zeroAndrew Jones1-1/+1
2024-02-09target/riscv: Use RISCVException as return type for all csr opsLIU Zhiwei1-43/+74
2024-02-09target/riscv/csr.c: use 'vlenb' instead of 'vlen'Daniel Henrique Barboza1-2/+2
2024-02-09target/riscv: Implement optional CSR mcontext of debug Sdtrig extensionAlvin Chang1-5/+31
2024-01-10target/riscv: Assert that the CSR numbers will be correctAlistair Francis1-1/+4
2024-01-10target/riscv: Not allow write mstatus_vs without RVVLIU Zhiwei1-1/+4
2024-01-05target/riscv: Fix mcycle/minstret increment behaviorXu Lu1-7/+7
2023-11-07target/riscv: Don't assume PMU counters are continuousRob Bradford1-2/+3
2023-11-07target/riscv: correct csr_ops[CSR_MSECCFG]Heinrich Schuchardt1-2/+5
2023-11-07target/riscv: add zicntr extension flag for TCGDaniel Henrique Barboza1-0/+4
2023-11-07Add epmp to extensions list and rename it to smepmpHimanshu Chauhan1-3/+3
2023-11-07target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal1-18/+178
2023-11-07target/riscv: Add M-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal1-28/+251
2023-11-07target/riscv: Without H-mode mask all HS mode inturrupts in mie.Rajnesh Kanwal1-1/+1
2023-11-07target/riscv: rename ext_icsr to ext_zicsrDaniel Henrique Barboza1-1/+1
2023-10-12target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.cDaniel Henrique Barboza1-0/+1
2023-09-11target/riscv: don't read CSR in riscv_csrrw_do64Nikita Shubin1-9/+15
2023-09-11target/riscv: Align the AIA model to v1.0 ratified specTommy Wu1-2/+5
2023-09-11target/riscv: Update CSR bits name for svadu extensionWeiwei Li1-6/+6
2023-09-11target/riscv: Implement WARL behaviour for mcountinhibit/mcounterenRob Bradford1-2/+9
2023-09-08riscv: spelling fixesMichael Tokarev1-2/+2
2023-08-31target/helpers: Remove unnecessary 'qemu/main-loop.h' headerPhilippe Mathieu-Daudé1-1/+0
2023-07-10target/riscv: update cur_pmbase/pmmask based on mode affected by MPRVWeiwei Li1-7/+20
2023-07-10target/riscv: Remove redundant assignment to SXLWeiwei Li1-4/+0
2023-07-10target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabledWeiwei Li1-6/+4
2023-06-13target/riscv: smstateen check for fcsrMayuresh Chitale1-0/+15
2023-06-13target/riscv: Update cur_pmmask/base when xl changesWeiwei Li1-1/+8
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