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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-24 12:08:48 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-01 17:28:14 -0800 |
| commit | 6f3eb1a3c82d18e5d03d25ec582f3b19ab7df203 (patch) | |
| tree | 77bded0fe777645127247f45eb0fa0bc5c18a4f3 /target/riscv/csr.c | |
| parent | 73ec0ead67ca8b4b10132b033b7388d0718b2353 (diff) | |
| download | qemu-6f3eb1a3c82d18e5d03d25ec582f3b19ab7df203.zip qemu-6f3eb1a3c82d18e5d03d25ec582f3b19ab7df203.tar.gz qemu-6f3eb1a3c82d18e5d03d25ec582f3b19ab7df203.tar.bz2 | |
target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg
henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224040852.37109-3-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'target/riscv/csr.c')
| -rw-r--r-- | target/riscv/csr.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b20b00a..b86c1aa 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1956,7 +1956,11 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno, return ret; } - *val = env->henvcfg; + /* + * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 + * henvcfg.stce is read_only 0 when menvcfg.stce = 0 + */ + *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | env->menvcfg); return RISCV_EXCP_NONE; } @@ -1972,7 +1976,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, } if (riscv_cpu_mxl(env) == MXL_RV64) { - mask |= HENVCFG_PBMTE | HENVCFG_STCE; + mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE); } env->henvcfg = (env->henvcfg & ~mask) | (val & mask); @@ -1990,14 +1994,15 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, return ret; } - *val = env->henvcfg >> 32; + *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | + env->menvcfg)) >> 32; return RISCV_EXCP_NONE; } static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, target_ulong val) { - uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE; + uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE); uint64_t valh = (uint64_t)val << 32; RISCVException ret; |