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csr.c
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Author
Files
Lines
2023-07-10
target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV
Weiwei Li
1
-7
/
+20
2023-07-10
target/riscv: Remove redundant assignment to SXL
Weiwei Li
1
-4
/
+0
2023-07-10
target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled
Weiwei Li
1
-6
/
+4
2023-06-13
target/riscv: smstateen check for fcsr
Mayuresh Chitale
1
-0
/
+15
2023-06-13
target/riscv: Update cur_pmmask/base when xl changes
Weiwei Li
1
-1
/
+8
2023-06-13
target/riscv: rework write_misa()
Daniel Henrique Barboza
1
-27
/
+24
2023-05-05
target/riscv: Restore the predicate() NULL check behavior
Bin Meng
1
-2
/
+9
2023-05-05
target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
Richard Henderson
1
-5
/
+1
2023-05-05
target/riscv: Reduce overhead of MSTATUS_SUM change
Fei Wu
1
-2
/
+1
2023-05-05
target/riscv: Add a general status enum for extensions
LIU Zhiwei
1
-7
/
+7
2023-05-05
target/riscv: fix H extension TVM trap
Yi Chen
1
-21
/
+35
2023-05-05
target/riscv: Legalize MPP value in write_mstatus
Weiwei Li
1
-0
/
+32
2023-05-05
target/riscv: Fix lines with over 80 characters
Weiwei Li
1
-17
/
+21
2023-05-05
target/riscv: Fix format for comments
Weiwei Li
1
-3
/
+3
2023-05-05
target/riscv: Remove riscv_cpu_virt_enabled()
Weiwei Li
1
-23
/
+23
2023-05-05
target/riscv: add support for Zcmt extension
Weiwei Li
1
-2
/
+34
2023-05-05
target/riscv: Simplify arguments for riscv_csrrw_check
Weiwei Li
1
-8
/
+4
2023-05-05
target/riscv: Simplify type conversion for CPURISCVState
Weiwei Li
1
-24
/
+11
2023-05-05
target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
Weiwei Li
1
-28
/
+12
2023-03-07
includes: move tb_flush into its own header
Alex Bennée
1
-0
/
+1
2023-03-06
riscv: Allow user to set the satp mode
Alexandre Ghiti
1
-7
/
+5
2023-03-06
riscv: Change type of valid_vm_1_10_[32|64] to bool
Alexandre Ghiti
1
-10
/
+11
2023-03-01
Merge patch series "RISCVCPUConfig related cleanups"
Palmer Dabbelt
1
-61
/
+48
2023-03-01
target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig
Daniel Henrique Barboza
1
-23
/
+9
2023-03-01
target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers
Daniel Henrique Barboza
1
-38
/
+12
2023-03-01
target/riscv/csr.c: simplify mctr()
Daniel Henrique Barboza
1
-3
/
+2
2023-03-01
target/riscv/csr.c: use env_archcpu() in ctr()
Daniel Henrique Barboza
1
-2
/
+1
2023-03-01
Merge patch series "target/riscv: Add support for Svadu extension"
Palmer Dabbelt
1
-6
/
+20
2023-03-01
target/riscv: Add csr support for svadu
Weiwei Li
1
-6
/
+11
2023-03-01
target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and h...
Weiwei Li
1
-4
/
+9
2023-03-01
target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc...
Weiwei Li
1
-2
/
+6
2023-03-01
Merge patch series "target/riscv: Various fixes to gdbstub and CSR access"
Palmer Dabbelt
1
-160
/
+181
2023-03-01
target/riscv: Group all predicate() routines together
Bin Meng
1
-90
/
+87
2023-03-01
target/riscv: Drop priv level check in mseccfg predicate()
Bin Meng
1
-1
/
+1
2023-03-01
target/riscv: Allow debugger to access sstc CSRs
Bin Meng
1
-5
/
+14
2023-03-01
target/riscv: Allow debugger to access {h, s}stateen CSRs
Bin Meng
1
-2
/
+20
2023-03-01
target/riscv: Allow debugger to access seed CSR
Bin Meng
1
-0
/
+4
2023-03-01
target/riscv: Allow debugger to access user timer and counter CSRs
Bin Meng
1
-0
/
+4
2023-03-01
target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64
Bin Meng
1
-15
/
+9
2023-03-01
target/riscv: Simplify getting RISCVCPU pointer from env
Bin Meng
1
-24
/
+12
2023-03-01
target/riscv: Simplify {read, write}_pmpcfg() a little bit
Bin Meng
1
-2
/
+2
2023-03-01
target/riscv: Use 'bool' type for read_only
Bin Meng
1
-1
/
+1
2023-03-01
target/riscv: Coding style fixes in csr.c
Bin Meng
1
-30
/
+32
2023-03-01
target/riscv: Use g_assert() for the predicate() NULL check
Bin Meng
1
-5
/
+1
2023-03-01
target/riscv: Add some comments to clarify the priority policy of riscv_csrrw...
Bin Meng
1
-1
/
+10
2023-03-01
Merge patch series "target/riscv: Some updates to float point related extensi...
Palmer Dabbelt
1
-2
/
+1
2023-03-01
target/riscv: Simplify check for Zve32f and Zve64f
Weiwei Li
1
-2
/
+1
2023-03-01
target/riscv: remove RISCV_FEATURE_MMU
Daniel Henrique Barboza
1
-2
/
+2
2023-03-01
target/riscv: remove RISCV_FEATURE_PMP
Daniel Henrique Barboza
1
-1
/
+1
2023-03-01
target/riscv: remove RISCV_FEATURE_EPMP
Daniel Henrique Barboza
1
-1
/
+1
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