aboutsummaryrefslogtreecommitdiff
path: root/target/riscv/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2023-03-06riscv: Introduce satp mode hw capabilitiesAlexandre Ghiti1-2/+6
2023-03-06riscv: Allow user to set the satp modeAlexandre Ghiti1-0/+21
2023-03-05target/riscv: implement Zicbom extensionChristoph Muellner1-0/+2
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner1-0/+2
2023-03-01Merge patch series "target/riscv: Add support for Svadu extension"Palmer Dabbelt1-0/+1
2023-03-01target/riscv: Add csr support for svaduWeiwei Li1-0/+1
2023-03-01target/riscv: Add support for Zicond extensionWeiwei Li1-0/+1
2023-03-01Merge patch series "target/riscv: Some updates to float point related extensi...Palmer Dabbelt1-0/+3
2023-03-01target/riscv: Add cfg properties for Zv* extensionsWeiwei Li1-0/+3
2023-03-01target/riscv/cpu: remove CPUArchState::features and friendsDaniel Henrique Barboza1-12/+0
2023-03-01target/riscv: remove RISCV_FEATURE_MMUDaniel Henrique Barboza1-7/+0
2023-03-01target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza1-1/+0
2023-03-01target/riscv: remove RISCV_FEATURE_EPMPDaniel Henrique Barboza1-1/+0
2023-03-01target/riscv: remove RISCV_FEATURE_DEBUGDaniel Henrique Barboza1-1/+0
2023-03-01target/riscv: allow MISA writes as experimentalDaniel Henrique Barboza1-1/+1
2023-03-01target/riscv: introduce riscv_cpu_cfg()Daniel Henrique Barboza1-0/+5
2023-02-27target/riscv/cpu: Move Floating-Point fields closerPhilippe Mathieu-Daudé1-3/+3
2023-02-27target/cpu: Restrict do_transaction_failed() handlers to sysemuPhilippe Mathieu-Daudé1-5/+5
2023-02-27target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemuPhilippe Mathieu-Daudé1-1/+1
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner1-0/+1
2023-02-07RISC-V: Add initial support for T-Head C906Christoph Müllner1-0/+1
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner1-0/+1
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner1-0/+1
2023-02-07RISC-V: Adding T-Head MemPair extensionChristoph Müllner1-0/+1
2023-02-07RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner1-0/+1
2023-02-07RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner1-0/+1
2023-02-07RISC-V: Adding XTheadBs ISA extensionChristoph Müllner1-0/+1
2023-02-07RISC-V: Adding XTheadBb ISA extensionChristoph Müllner1-0/+1
2023-02-07RISC-V: Adding XTheadBa ISA extensionChristoph Müllner1-0/+1
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner1-0/+1
2023-02-07RISC-V: Adding XTheadCmo ISA extensionChristoph Müllner1-0/+1
2023-01-20target/riscv/cpu: set cpu->cfg in register_cpu_props()Daniel Henrique Barboza1-0/+4
2023-01-20hw/char: riscv_htif: Move registers from CPUArchState to HTIFStateBin Meng1-4/+0
2023-01-06RISC-V: Add Zawrs ISA extension supportChristoph Muellner1-0/+1
2023-01-06target/riscv: Add itrigger_enabled field to CPURISCVStateLIU Zhiwei1-0/+1
2023-01-06target/riscv: Add itrigger support when icount is enabledLIU Zhiwei1-0/+2
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei1-0/+2
2023-01-06target/riscv: Add smstateen supportMayuresh Chitale1-0/+4
2022-12-16target/riscv: Convert to 3-phase resetPeter Maydell1-2/+2
2022-10-06dump: Replace opaque DumpState pointer with a typed oneJanosch Frank1-2/+2
2022-09-27target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRsFrank Chang1-1/+5
2022-09-27target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang1-1/+1
2022-09-27target/riscv: Set the CPU resetvec directlyAlistair Francis1-2/+1
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra1-0/+25
2022-09-07target/riscv: Add vstimecmp supportAtish Patra1-0/+4
2022-09-07target/riscv: Add stimecmp supportAtish Patra1-0/+5
2022-09-07hw/intc: Move mtimer/mtimecmp to aclintAtish Patra1-2/+0
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel1-2/+2
2022-09-07target/riscv: Add Zihintpause supportDao Lu1-0/+1
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen1-0/+2
generated by cgit v1.1 at 2024-12-29 13:36:06 +0000