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| author | Yueh-Ting (eop) Chen <eop.chen@sifive.com> | 2022-06-20 06:51:02 +0000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-09-07 09:18:32 +0200 |
| commit | 355d5584de1129eec1c4043fdee1335010cfabb6 (patch) | |
| tree | c7b76a04820f83308a2d9019d5b536dc41c8562c /target/riscv/cpu.h | |
| parent | 079520033facc70beee5eedee8d7a27a2a9261b4 (diff) | |
| download | qemu-355d5584de1129eec1c4043fdee1335010cfabb6.zip qemu-355d5584de1129eec1c4043fdee1335010cfabb6.tar.gz qemu-355d5584de1129eec1c4043fdee1335010cfabb6.tar.bz2 | |
target/riscv: rvv: Add mask agnostic for vv instructions
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between mask policies. Setting agnostic elements to
all 1s allows QEMU to express this.
This is the first commit regarding the optional mask agnostic
behavior. Follow-up commits will add this optional behavior
for all rvv instructions.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165570784143.17634.35095816584573691-1@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ffb1a18..561d7fa 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -439,6 +439,7 @@ struct RISCVCPUConfig { bool ext_zve64f; bool ext_zmmul; bool rvv_ta_all_1s; + bool rvv_ma_all_1s; uint32_t mvendorid; uint64_t marchid; @@ -596,6 +597,7 @@ FIELD(TB_FLAGS, XL, 20, 2) FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) FIELD(TB_FLAGS, VTA, 24, 1) +FIELD(TB_FLAGS, VMA, 25, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) |