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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-01-31 21:20:04 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-02-07 08:19:23 +1000 |
| commit | fa134585462897fc70a01d7b585fbc60371a7d17 (patch) | |
| tree | 76337e60c033481ca182623cfd1cb9f1e7337772 /target/riscv/cpu.h | |
| parent | 426c049196efcdfc57511f779ec0416dd95a9cce (diff) | |
| download | qemu-fa134585462897fc70a01d7b585fbc60371a7d17.zip qemu-fa134585462897fc70a01d7b585fbc60371a7d17.tar.gz qemu-fa134585462897fc70a01d7b585fbc60371a7d17.tar.bz2 | |
RISC-V: Adding XTheadBs ISA extension
This patch adds support for the XTheadBs ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-6-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index be86c2f..876eaeb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -475,6 +475,7 @@ struct RISCVCPUConfig { /* Vendor-specific custom extensions */ bool ext_xtheadba; bool ext_xtheadbb; + bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadsync; bool ext_XVentanaCondOps; |