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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-01-31 21:20:05 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-02-07 08:19:23 +1000 |
| commit | 3290933853c2c8a4a50a990cc395471097f0a173 (patch) | |
| tree | 7071c8681f3da94cc89a295e4dfe7c7e4ef87bc3 /target/riscv/cpu.h | |
| parent | fa134585462897fc70a01d7b585fbc60371a7d17 (diff) | |
| download | qemu-3290933853c2c8a4a50a990cc395471097f0a173.zip qemu-3290933853c2c8a4a50a990cc395471097f0a173.tar.gz qemu-3290933853c2c8a4a50a990cc395471097f0a173.tar.bz2 | |
RISC-V: Adding XTheadCondMov ISA extension
This patch adds support for the XTheadCondMov ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-7-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 876eaeb..a313e02 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -477,6 +477,7 @@ struct RISCVCPUConfig { bool ext_xtheadbb; bool ext_xtheadbs; bool ext_xtheadcmo; + bool ext_xtheadcondmov; bool ext_xtheadsync; bool ext_XVentanaCondOps; |