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path: root/target/riscv/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2020-06-03target/riscv: Add the lowRISC Ibex CPUAlistair Francis1-0/+1
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis1-1/+0
2020-06-03target/riscv: Remove the deprecated CPUsAlistair Francis1-7/+0
2020-04-29target/riscv: Add a sifive-e34 cpu typeCorey Wharton1-0/+1
2020-03-19Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell1-1/+1
2020-03-17cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell1-1/+1
2020-03-17gdbstub: extend GByteArray to read register helpersAlex Bennée1-1/+1
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel1-0/+5
2020-02-27target/riscv: Allow enabling the Hypervisor extensionAlistair Francis1-0/+1
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis1-0/+10
2020-02-27target/riscv: Implement second stage MMUAlistair Francis1-0/+1
2020-02-27target/riscv: Only set TB flags with FP status if enabledAlistair Francis1-1/+4
2020-02-27target/riscv: Add virtual register swapping functionAlistair Francis1-0/+11
2020-02-27target/riscv: Add the force HS exception modeAlistair Francis1-0/+2
2020-02-27target/riscv: Add the virtulisation modeAlistair Francis1-0/+4
2020-02-27target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis1-0/+21
2020-02-27target/riscv: Add the Hypervisor extensionAlistair Francis1-0/+1
2020-02-27target/riscv: Convert MIP CSR to target_ulongAlistair Francis1-1/+1
2020-01-16target/riscv: Fix tb->flags FS statusShihPo Hung1-4/+1
2019-11-14target/riscv: Remove atomic accesses to MIP CSRAlistair Francis1-9/+0
2019-10-28RISC-V: Implement cpu_do_transaction_failedPalmer Dabbelt1-2/+5
2019-09-17target/riscv: Use TB_FLAGS_MSTATUS_FS for floating pointAlistair Francis1-1/+1
2019-09-17target/riscv: Create function to test if FP is enabledAlistair Francis1-1/+5
2019-08-21hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster1-1/+1
2019-08-19target/riscv: rationalise softfloat includesAlex Bennée1-1/+1
2019-06-25RISC-V: Add support for the Zicsr extensionPalmer Dabbelt1-0/+1
2019-06-25RISC-V: Add support for the Zifencei extensionPalmer Dabbelt1-0/+1
2019-06-25target/riscv: Add support for disabling/enabling CountersAlistair Francis1-0/+1
2019-06-25target/riscv: Remove user version informationAlistair Francis1-2/+0
2019-06-24target/riscv: Add the privledge spec version 1.11.0Alistair Francis1-0/+1
2019-06-24target/riscv: Restructure deprecatd CPUsAlistair Francis1-6/+7
2019-06-23RISC-V: Check PMP during Page Table WalksHesham Almatary1-0/+1
2019-06-23target/riscv: Implement riscv_cpu_unassigned_accessMichael Clark1-0/+2
2019-06-23target/riscv: Allow setting ISA extensions via CPU propsAlistair Francis1-0/+11
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster1-1/+0
2019-06-10cpu: Remove CPU_COMMONRichard Henderson1-3/+0
2019-06-10cpu: Introduce CPUNegativeOffsetStateRichard Henderson1-0/+1
2019-06-10cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson1-2/+0
2019-06-10target/riscv: Use env_cpu, env_archcpuRichard Henderson1-5/+0
2019-06-10cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson1-1/+0
2019-06-10cpu: Define ArchCPURichard Henderson1-0/+1
2019-06-10cpu: Define CPUArchState with typedefRichard Henderson1-2/+2
2019-06-10tcg: Split out target/arch/cpu-param.hRichard Henderson1-17/+4
2019-05-24target/riscv: Add a base 32 and 64 bit CPUAlistair Francis1-0/+2
2019-05-24target/riscv: Create settable CPU propertiesAlistair Francis1-0/+8
2019-05-10target/riscv: Convert to CPUClass::tlb_fillRichard Henderson1-2/+3
2019-04-18target: Simplify how the TARGET_cpu_list() printMarkus Armbruster1-1/+1
2019-03-19RISC-V: linux-user support for RVE ABIKito Cheng1-0/+4
2019-03-19RISC-V: Allow interrupt controllers to claim interruptsMichael Clark1-0/+2
2019-03-19RISC-V: Add hooks to use the gdb xml files.Jim Wilson1-0/+2
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