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| author | Alistair Francis <alistair.francis@wdc.com> | 2020-05-06 13:03:25 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-06-03 09:11:51 -0700 |
| commit | 65a117da6ec5f0226952368d544cfb5c2a1dcead (patch) | |
| tree | 9a6fd37ddefdc9219fd434ea6395523de98471ca /target/riscv/cpu.h | |
| parent | 26cd0362dd43a32fc9a917f5c00b20e9dafa93be (diff) | |
| download | qemu-65a117da6ec5f0226952368d544cfb5c2a1dcead.zip qemu-65a117da6ec5f0226952368d544cfb5c2a1dcead.tar.gz qemu-65a117da6ec5f0226952368d544cfb5c2a1dcead.tar.bz2 | |
target/riscv: Remove the deprecated CPUs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d0e7f5b..76b98d7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -40,13 +40,6 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") -/* Deprecated */ -#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu") -#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") -#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") -#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu") -#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1") -#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0") #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) |