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| author | Michael Clark <mjc@sifive.com> | 2019-05-17 15:11:06 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-06-23 23:44:41 -0700 |
| commit | cbf5827693addaff4e4d2102afedbf078a204eb2 (patch) | |
| tree | e857c066240d7706ccd11e822d53aefdd049faec /target/riscv/cpu.h | |
| parent | 49db9fa1fd7c252596b53cf80876e06f407d09ed (diff) | |
| download | qemu-cbf5827693addaff4e4d2102afedbf078a204eb2.zip qemu-cbf5827693addaff4e4d2102afedbf078a204eb2.tar.gz qemu-cbf5827693addaff4e4d2102afedbf078a204eb2.tar.bz2 | |
target/riscv: Implement riscv_cpu_unassigned_access
This patch adds support for the riscv_cpu_unassigned_access call
and will raise a load or store access fault.
Signed-off-by: Michael Clark <mjc@sifive.com>
[Changes by AF:
- Squash two patches and rewrite commit message
- Set baddr to the access address
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b47cde5..2e74331 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -259,6 +259,8 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void riscv_cpu_unassigned_access(CPUState *cpu, hwaddr addr, bool is_write, + bool is_exec, int unused, unsigned size); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); |