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Author
Files
Lines
2020-06-03
target/riscv: Add the lowRISC Ibex CPU
Alistair Francis
2
-0
/
+11
2020-06-03
target/riscv: Don't set PMP feature in the cpu init
Alistair Francis
1
-5
/
+0
2020-06-03
target/riscv: Disable the MMU correctly
Alistair Francis
1
-2
/
+3
2020-06-03
target/riscv: Don't overwrite the reset vector
Alistair Francis
1
-1
/
+2
2020-06-03
target/riscv: Drop support for ISA spec version 1.09.1
Alistair Francis
7
-200
/
+63
2020-06-03
target/riscv: Remove the deprecated CPUs
Alistair Francis
2
-35
/
+0
2020-04-29
target/riscv: Add a sifive-e34 cpu type
Corey Wharton
2
-0
/
+11
2020-04-29
riscv: Fix Stage2 SV32 page table walk
Anup Patel
1
-6
/
+1
2020-04-29
riscv: AND stage-1 and stage-2 protection flags
Alistair Francis
1
-3
/
+5
2020-04-29
riscv: Don't use stage-2 PTE lookup protection flags
Alistair Francis
1
-1
/
+2
2020-03-19
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...
Peter Maydell
2
-4
/
+5
2020-03-17
cpu: Use DeviceClass reset instead of a special CPUClass reset
Peter Maydell
2
-4
/
+5
2020-03-17
gdbstub: extend GByteArray to read register helpers
Alex Bennée
2
-11
/
+11
2020-03-16
target/riscv: Fix VS mode interrupts forwarding.
Rajnesh Kanwal
1
-1
/
+8
2020-03-16
target/riscv: Correctly implement TSR trap
Alistair Francis
1
-1
/
+1
2020-03-05
RISC-V: Add a missing "," in riscv_excp_names
Palmer Dabbelt
1
-2
/
+2
2020-02-27
target/riscv: Emulate TIME CSRs for privileged mode
Anup Patel
3
-4
/
+92
2020-02-27
target/riscv: Allow enabling the Hypervisor extension
Alistair Francis
2
-0
/
+6
2020-02-27
target/riscv: Add the MSTATUS_MPV_ISSET helper macro
Alistair Francis
4
-4
/
+15
2020-02-27
target/riscv: Add support for the 32-bit MSTATUSH CSR
Alistair Francis
6
-0
/
+62
2020-02-27
target/riscv: Set htval and mtval2 on execptions
Alistair Francis
1
-0
/
+10
2020-02-27
target/riscv: Raise the new execptions when 2nd stage translation fails
Alistair Francis
1
-6
/
+18
2020-02-27
target/riscv: Implement second stage MMU
Alistair Francis
2
-19
/
+175
2020-02-27
target/riscv: Allow specifying MMU stage
Alistair Francis
1
-9
/
+28
2020-02-27
target/riscv: Respect MPRV and SPRV for floating point ops
Alistair Francis
1
-1
/
+15
2020-02-27
target/riscv: Mark both sstatus and msstatus_hs as dirty
Alistair Francis
1
-0
/
+13
2020-02-27
target/riscv: Disable guest FP support based on virtual status
Alistair Francis
1
-0
/
+3
2020-02-27
target/riscv: Only set TB flags with FP status if enabled
Alistair Francis
1
-1
/
+4
2020-02-27
target/riscv: Remove the hret instruction
Alistair Francis
2
-6
/
+0
2020-02-27
target/riscv: Add hfence instructions
Alistair Francis
2
-9
/
+54
2020-02-27
target/riscv: Add Hypervisor trap return support
Alistair Francis
1
-10
/
+52
2020-02-27
target/riscv: Add hypvervisor trap support
Alistair Francis
1
-10
/
+59
2020-02-27
target/riscv: Generate illegal instruction on WFI when V=1
Alistair Francis
1
-2
/
+3
2020-02-27
target/ricsv: Flush the TLB on virtulisation mode changes
Alistair Francis
1
-0
/
+5
2020-02-27
target/riscv: Add support for virtual interrupt setting
Alistair Francis
1
-5
/
+28
2020-02-27
target/riscv: Extend the SIP CSR to support virtulisation
Alistair Francis
1
-1
/
+12
2020-02-27
target/riscv: Extend the MIE CSR to support virtulisation
Alistair Francis
1
-4
/
+20
2020-02-27
target/riscv: Set VS bits in mideleg for Hyp extension
Alistair Francis
1
-0
/
+3
2020-02-27
target/riscv: Add virtual register swapping function
Alistair Francis
3
-0
/
+79
2020-02-27
target/riscv: Add Hypervisor machine CSRs accesses
Alistair Francis
1
-0
/
+27
2020-02-27
target/riscv: Add Hypervisor virtual CSRs accesses
Alistair Francis
1
-0
/
+116
2020-02-27
target/riscv: Add Hypervisor CSR access functions
Alistair Francis
1
-2
/
+134
2020-02-27
target/riscv: Dump Hypervisor registers if enabled
Alistair Francis
1
-0
/
+33
2020-02-27
target/riscv: Print priv and virt in disas log
Alistair Francis
1
-0
/
+8
2020-02-27
target/riscv: Fix CSR perm checking for HS mode
Alistair Francis
1
-4
/
+14
2020-02-27
target/riscv: Add the force HS exception mode
Alistair Francis
3
-0
/
+26
2020-02-27
target/riscv: Add the virtulisation mode
Alistair Francis
3
-0
/
+25
2020-02-27
target/riscv: Rename the H irqs to VS irqs
Alistair Francis
2
-9
/
+9
2020-02-27
target/riscv: Add support for the new execption numbers
Alistair Francis
4
-20
/
+37
2020-02-27
target/riscv: Add the Hypervisor CSRs to CPUState
Alistair Francis
3
-18
/
+48
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