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Author
Files
Lines
2021-10-22
hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
Bin Meng
1
-4
/
+2
2021-10-22
hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
Bin Meng
1
-4
/
+2
2021-10-22
hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
Bin Meng
1
-4
/
+12
2021-10-22
hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
Bin Meng
1
-4
/
+2
2021-10-22
hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
Bin Meng
1
-4
/
+12
2021-10-22
hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ra...
Bin Meng
1
-16
/
+20
2021-10-22
hw/riscv: opentitan: Update to the latest build
Alistair Francis
1
-5
/
+17
2021-10-22
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
Richard Henderson
1
-1
/
+1
2021-10-22
hw/riscv: virt: Use machine->ram as the system memory
Mingwang Li
1
-4
/
+2
2021-10-07
hw/riscv: shakti_c: Mark as not user creatable
Alistair Francis
1
-0
/
+7
2021-09-21
hw/riscv: opentitan: Correct the USB Dev address
Alistair Francis
1
-1
/
+1
2021-09-21
hw/riscv: virt: Add optional ACLINT support to virt machine
Anup Patel
1
-1
/
+112
2021-09-21
hw/riscv: virt: Re-factor FDT generation
Anup Patel
1
-200
/
+327
2021-09-21
hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
Anup Patel
6
-24
/
+44
2021-09-21
hw/intc: Rename sifive_clint sources to riscv_aclint sources
Anup Patel
7
-12
/
+12
2021-09-21
sifive_u: Connect the SiFive PWM device
Alistair Francis
2
-1
/
+55
2021-09-21
hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
Alistair Francis
1
-0
/
+3
2021-09-21
hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
Alistair Francis
5
-5
/
+6
2021-09-21
hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines
Alistair Francis
1
-0
/
+8
2021-09-01
hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()
Peter Maydell
1
-13
/
+20
2021-09-01
hw/riscv: virt: Move flash node to root
Bin Meng
1
-1
/
+1
2021-09-01
hw/char: Add config for shakti uart
Vijai Kumar K
1
-4
/
+1
2021-08-26
arch_init.h: Don't include arch_init.h unnecessarily
Peter Maydell
4
-4
/
+0
2021-07-20
hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines
Philippe Mathieu-Daudé
2
-1
/
+6
2021-07-15
hw/riscv/boot: Check the error of fdt_pack()
Alistair Francis
1
-2
/
+4
2021-07-15
hw/riscv: opentitan: Add the flash alias
Alistair Francis
1
-0
/
+6
2021-07-15
hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
Alistair Francis
1
-0
/
+3
2021-07-15
hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned
Bin Meng
1
-2
/
+3
2021-07-15
hw/riscv: sifive_u: Correct the CLINT timebase frequency
Bin Meng
1
-2
/
+5
2021-06-24
hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
Alistair Francis
1
-3
/
+11
2021-06-08
hw/riscv: microchip_pfsoc: Support direct kernel boot
Bin Meng
1
-3
/
+78
2021-06-08
hw/riscv: Use macros for BIOS image names
Bin Meng
3
-12
/
+6
2021-06-08
hw/riscv: Support the official PLIC DT bindings
Bin Meng
2
-2
/
+10
2021-06-08
hw/riscv: Support the official CLINT DT bindings
Bin Meng
3
-3
/
+15
2021-06-08
hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper
Bin Meng
1
-2
/
+5
2021-06-08
hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
Bin Meng
1
-3
/
+3
2021-05-11
hw/riscv: Fix OT IBEX reset vector
Alexander Wagner
1
-1
/
+1
2021-05-11
hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
Alistair Francis
1
-0
/
+1
2021-05-11
hw/opentitan: Update the interrupt layout
Alistair Francis
1
-4
/
+4
2021-05-11
hw/riscv: Connect Shakti UART to Shakti platform
Vijai Kumar K
1
-0
/
+8
2021-05-11
riscv: Add initial support for Shakti C machine
Vijai Kumar K
3
-0
/
+184
2021-05-11
hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
Bin Meng
1
-1
/
+1
2021-05-02
Do not include exec/address-spaces.h if it's not really necessary
Thomas Huth
2
-2
/
+0
2021-05-02
hw: Do not include qemu/log.h if it is not necessary
Thomas Huth
6
-6
/
+0
2021-05-02
hw: Do not include hw/irq.h if it is not necessary
Thomas Huth
1
-1
/
+0
2021-03-22
hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
Bin Meng
1
-0
/
+6
2021-03-22
hw/riscv: allow ramfb on virt
Asherah Connor
1
-0
/
+3
2021-03-22
hw/riscv: Add fw_cfg support to virt
Asherah Connor
2
-0
/
+31
2021-03-11
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-docs-xen-upda...
Peter Maydell
1
-10
/
+10
2021-03-10
hw/riscv: migrate fdt field to generic MachineState
Alex Bennée
1
-10
/
+10
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