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| author | Alexander Wagner <alexander.wagner@ulal.de> | 2021-04-20 10:00:08 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-05-11 20:02:07 +1000 |
| commit | d11e316d843b2d370a547700407947356e4117cb (patch) | |
| tree | bf9caba80046dab9023eeb0ab6bb870e85a34bd4 /hw/riscv | |
| parent | f9e580c13ae0d42cf8989063254300c59166ffed (diff) | |
| download | qemu-d11e316d843b2d370a547700407947356e4117cb.zip qemu-d11e316d843b2d370a547700407947356e4117cb.tar.gz qemu-d11e316d843b2d370a547700407947356e4117cb.tar.bz2 | |
hw/riscv: Fix OT IBEX reset vector
The IBEX documentation [1] specifies the reset vector to be "the most
significant 3 bytes of the boot address and the reset value (0x80) as
the least significant byte".
[1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst
Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210420080008.119798-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/opentitan.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 557d737..7545dcd 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -119,7 +119,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) &error_abort); object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, &error_abort); - object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort); + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); /* Boot ROM */ |