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2021-10-279pfs: deduplicate iounit codeChristian Schoenebeck1-21/+20
2021-10-279pfs: fix wrong I/O block size in RgetattrChristian Schoenebeck1-1/+20
2021-10-26Merge remote-tracking branch 'remotes/dagrh/tags/pull-virtiofs-20211026' into...Richard Henderson3-45/+58
2021-10-25virtiofsd: Error on bad socket group nameDr. David Alan Gilbert1-0/+7
2021-10-25virtiofsd: Add a helper to stop all queuesVivek Goyal1-9/+13
2021-10-25virtiofsd: Add a helper to send element on virtqueueVivek Goyal1-27/+18
2021-10-25virtiofsd: Remove unused virtio_fs_config definitionVivek Goyal1-6/+0
2021-10-25virtiofsd: xattr mapping add a new type "unsupported"Vivek Goyal2-3/+20
2021-10-23Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull...Richard Henderson11-90/+87
2021-10-23analyze-migration.py: fix extract contents ('-x') errorsLaurent Vivier1-2/+2
2021-10-23analyze-migration.py: fix a long standing typoLaurent Vivier1-1/+1
2021-10-23README: Fix some documentation URLsGreg Kurz1-7/+7
2021-10-23hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse deviceTong Ho1-6/+12
2021-10-23hw/nvram: Fix Memory Leak in Xilinx Versal eFuse deviceTong Ho1-5/+15
2021-10-23hw/nvram: Fix Memory Leak in Xilinx eFuse QOMTong Ho1-3/+6
2021-10-23softmmu/physmem.c: Fix typo in commentGreg Kurz1-1/+1
2021-10-23MAINTAINERS: Add myself as reviewer of 'Machine core' APIPhilippe Mathieu-Daudé1-0/+1
2021-10-22Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202...Richard Henderson28-779/+720
2021-10-22Merge remote-tracking branch 'remotes/kraxel/tags/seabios-20211022-pull-reque...Richard Henderson13-0/+0
2021-10-22disas/nios2: Simplify endianess conversionPhilippe Mathieu-Daudé3-26/+5
2021-10-22disas/nios2: Fix style in print_insn_nios2()Philippe Mathieu-Daudé1-28/+27
2021-10-22po: update turkish translationOğuz Ersen1-13/+12
2021-10-22Merge remote-tracking branch 'remotes/clg/tags/pull-aspeed-20211022' into sta...Richard Henderson5-5/+91
2021-10-22Merge remote-tracking branch 'remotes/vivier-m68k/tags/q800-pull-request' int...Richard Henderson4-5/+189
2021-10-22hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
2021-10-22hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
2021-10-22hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+12
2021-10-22hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
2021-10-22hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+12
2021-10-22hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ra...Bin Meng1-16/+20
2021-10-22hw/intc: sifive_plic: Cleanup the irq_request functionAlistair Francis1-6/+4
2021-10-22hw/intc: sifive_plic: Cleanup the realize functionAlistair Francis1-21/+24
2021-10-22hw/intc: sifive_plic: Move the propertiesAlistair Francis1-15/+15
2021-10-22hw/intc: Remove the Ibex PLICAlistair Francis2-308/+0
2021-10-22hw/riscv: opentitan: Update to the latest buildAlistair Francis2-8/+20
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson3-20/+25
2021-10-22target/riscv: Use riscv_csrrw_debug for cpu_dumpRichard Henderson1-44/+45
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson3-52/+97
2021-10-22target/riscv: Use gen_unary_per_ol for RVBRichard Henderson2-17/+32
2021-10-22target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson1-1/+6
2021-10-22target/riscv: Use gen_arith_per_ol for RVMRichard Henderson2-3/+39
2021-10-22update seabios binariesGerd Hoffmann12-0/+0
2021-10-22update seabios to master branch snapshotGerd Hoffmann1-0/+0
2021-10-22speed/sdhci: Add trace eventsCédric Le Goater2-0/+9
2021-10-22aspeed/smc: Use a container for the flash mmio address spaceCédric Le Goater2-5/+8
2021-10-22aspeed: Add support for the fp5280g2-bmc boardJohn Wang1-0/+74
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson4-43/+62
2021-10-22target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson1-14/+17
2021-10-22target/riscv: Properly check SEW in amo_opRichard Henderson1-12/+14
2021-10-22target/riscv: Use REQUIRE_64BIT in amo_check64Richard Henderson1-1/+2