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2018-12-20sifive_uart: Implement interrupt pending registerNathaniel Graff1-5/+19
2018-12-20RISC-V: Enable second UART on sifive_e and sifive_uMichael Clark2-6/+4
2018-12-20RISC-V: Fix PLIC pending bitfield readsMichael Clark1-1/+1
2018-12-20RISC-V: Fix CLINT timecmp low 32-bit writesMichael Clark1-4/+4
2018-12-20sifive_u: Set 'clock-frequency' DT property for SiFive UARTAnup Patel1-0/+2
2018-12-20sifive_u: Add clock DT node for GEM ethernetAnup Patel1-1/+17
2018-12-20hw/riscv/virt: Connect the gpex PCIeAlistair Francis1-1/+130
2018-12-20hw/riscv/virt: Adjust memory layout spacingAlistair Francis1-8/+8
2018-11-13hw/riscv/virt: Free the test device tree node nameAlistair Francis1-0/+1
2018-11-08riscv: spike: Fix memory leak in the board initAlistair Francis1-3/+3
2018-10-17RISC-V: Don't add NULL bootargs to device-treeMichael Clark3-4/+10
2018-10-17RISC-V: Add missing free for plic_hart_configMichael Clark1-0/+2
2018-10-17RISC-V: Allow setting and clearing multiple irqsMichael Clark2-6/+6
2018-09-25Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-09-24' into...Peter Maydell4-5/+5
2018-09-24Drop "qemu:" prefix from error_report() argumentsMao Zhongyi4-5/+5
2018-09-05hw/riscv/spike: Set the soc device tree node as a simple-busAlistair Francis1-1/+1
2018-09-05hw/riscv/virtio: Set the soc device tree node as a simple-busAlistair Francis1-1/+1
2018-09-04RISC-V: Use atomic_cmpxchg to update PLIC bitmapsMichael Clark1-27/+22
2018-07-19spike: Fix crash when introspecting the deviceAlistair Francis1-6/+4
2018-07-19riscv_hart: Fix crash when introspecting the deviceAlistair Francis1-4/+3
2018-07-19virt: Fix crash when introspecting the deviceAlistair Francis1-3/+2
2018-07-19sifive_u: Fix crash when introspecting the deviceAlistair Francis1-8/+7
2018-07-19sifive_e: Fix crash when introspecting the deviceAlistair Francis1-6/+6
2018-07-05hw/riscv/sifive_u: Connect the Cadence GEM Ethernet deviceAlistair Francis1-0/+50
2018-07-05hw/riscv/sifive_u: Move the uart device tree node under /soc/Alistair Francis1-1/+1
2018-07-05hw/riscv/sifive_u: Set the interrupt controller number of interruptsAlistair Francis1-1/+1
2018-07-05hw/riscv/sifive_u: Set the soc device tree node as a simple-busAlistair Francis1-1/+1
2018-07-05hw/riscv/sifive_plic: Use gpios instead of irqsAlistair Francis4-11/+9
2018-07-05hw/riscv/sifive_e: Create a SiFive E SoC objectAlistair Francis1-25/+69
2018-07-05hw/riscv/sifive_u: Create a SiFive U SoC objectAlistair Francis1-22/+65
2018-07-02hw/riscv: Use the IEC binary prefix definitionsPhilippe Mathieu-Daudé1-1/+2
2018-06-01hw: Do not include "exec/address-spaces.h" if it is not necessaryPhilippe Mathieu-Daudé1-1/+0
2018-05-10Merge remote-tracking branch 'remotes/riscv/tags/riscv-qemu-2.13-minor-fixes-...Peter Maydell1-4/+8
2018-05-09riscv: htif: increase the priority of the htif subregionKONRAD Frederic1-2/+3
2018-05-09riscv: spike: allow base == 0KONRAD Frederic1-2/+5
2018-05-06RISC-V: Mark ROM read-only after copying in codeMichael Clark4-82/+101
2018-05-06RISC-V: Remove EM_RISCV ELF_MACHINE indirectionMichael Clark4-4/+4
2018-05-06RISC-V: Remove unused class definitionsMichael Clark5-101/+0
2018-05-06RISC-V: Remove identity_translate from load_elfMichael Clark4-24/+4
2018-05-06RISC-V: Use ROM base address and size from memmapMichael Clark1-2/+2
2018-05-06RISC-V: Make virt board description match spikeMichael Clark1-1/+1
2018-05-06RISC-V: Replace hardcoded constants with enum valuesMichael Clark4-12/+15
2018-04-26Change references to serial_hds[] to serial_hd()Peter Maydell4-7/+7
2018-03-07RISC-V Build InfrastructureMichael Clark1-0/+11
2018-03-07SiFive Freedom U Series RISC-V MachineMichael Clark1-0/+339
2018-03-07SiFive Freedom E Series RISC-V MachineMichael Clark1-0/+234
2018-03-07SiFive RISC-V PRCI BlockMichael Clark1-0/+89
2018-03-07SiFive RISC-V UART DeviceMichael Clark1-0/+176
2018-03-07RISC-V VirtIO MachineMichael Clark1-0/+420
2018-03-07SiFive RISC-V Test FinisherMichael Clark1-0/+93