diff options
| author | Michael Clark <mjc@sifive.com> | 2018-12-14 00:18:54 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-12-20 12:08:43 -0800 |
| commit | e41848e5c9245947c09fb0cf3e160ec9350907f4 (patch) | |
| tree | e3013e1c229a2d25f835861141232efea0e6971d /hw/riscv | |
| parent | ef9e41df680a494dec92fe8d166cb2bc531b29a4 (diff) | |
| download | qemu-e41848e5c9245947c09fb0cf3e160ec9350907f4.zip qemu-e41848e5c9245947c09fb0cf3e160ec9350907f4.tar.gz qemu-e41848e5c9245947c09fb0cf3e160ec9350907f4.tar.bz2 | |
RISC-V: Fix PLIC pending bitfield reads
The address calculation for the pending bitfield had
a copy paste bug. This bug went unnoticed because the Linux
PLIC driver does not read the pending bitfield, rather it
reads pending interrupt numbers from the claim register
and writes acknowledgements back to the claim register.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Reported-by: Vincent Siles <vincent.siles@ens-lyon.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/sifive_plic.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 9cf9a1f..d12ec3f 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -214,7 +214,7 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size) } else if (addr >= plic->pending_base && /* 1 bit per source */ addr < plic->pending_base + (plic->num_sources >> 3)) { - uint32_t word = (addr - plic->priority_base) >> 2; + uint32_t word = (addr - plic->pending_base) >> 2; if (RISCV_DEBUG_PLIC) { qemu_log("plic: read pending: word=%d value=%d\n", word, plic->pending[word]); |