diff options
| author | Anup Patel <anup@brainfault.org> | 2018-12-13 18:36:17 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-12-20 12:03:26 -0800 |
| commit | 6c60757eb667c5c5b4a1f6ce3eff874b83bcd734 (patch) | |
| tree | 2053e94bad8cd248e8e29c37f64ac612b3322468 /hw/riscv | |
| parent | fe93582cf52ee67f6ab5a59051d354344010cfdc (diff) | |
| download | qemu-6c60757eb667c5c5b4a1f6ce3eff874b83bcd734.zip qemu-6c60757eb667c5c5b4a1f6ce3eff874b83bcd734.tar.gz qemu-6c60757eb667c5c5b4a1f6ce3eff874b83bcd734.tar.bz2 | |
sifive_u: Set 'clock-frequency' DT property for SiFive UART
The 'clock-frequency' DT property is required by U-Boot to compute
the divider value. This patch sets the 'clock-frequency' DT property
of the SiFive UART device tree node (similar to virt machine).
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/sifive_u.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 5c41ee5..849fa2e 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -241,6 +241,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_UART0].base, 0x0, memmap[SIFIVE_U_UART0].size); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_CLOCK_FREQ / 2); qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1); |