riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-12-20	sifive_uart: Implement interrupt pending register	Nathaniel Graff	1	-5/+19
2018-12-20	RISC-V: Enable second UART on sifive_e and sifive_u	Michael Clark	2	-6/+4
2018-12-20	RISC-V: Fix PLIC pending bitfield reads	Michael Clark	1	-1/+1
2018-12-20	RISC-V: Fix CLINT timecmp low 32-bit writes	Michael Clark	1	-4/+4
2018-12-20	sifive_u: Set 'clock-frequency' DT property for SiFive UART	Anup Patel	1	-0/+2
2018-12-20	sifive_u: Add clock DT node for GEM ethernet	Anup Patel	1	-1/+17
2018-12-20	hw/riscv/virt: Connect the gpex PCIe	Alistair Francis	1	-1/+130
2018-12-20	hw/riscv/virt: Adjust memory layout spacing	Alistair Francis	1	-8/+8
2018-11-13	hw/riscv/virt: Free the test device tree node name	Alistair Francis	1	-0/+1
2018-11-08	riscv: spike: Fix memory leak in the board init	Alistair Francis	1	-3/+3
2018-10-17	RISC-V: Don't add NULL bootargs to device-tree	Michael Clark	3	-4/+10
2018-10-17	RISC-V: Add missing free for plic_hart_config	Michael Clark	1	-0/+2
2018-10-17	RISC-V: Allow setting and clearing multiple irqs	Michael Clark	2	-6/+6
2018-09-25	Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-09-24' into...	Peter Maydell	4	-5/+5
2018-09-24	Drop "qemu:" prefix from error_report() arguments	Mao Zhongyi	4	-5/+5
2018-09-05	hw/riscv/spike: Set the soc device tree node as a simple-bus	Alistair Francis	1	-1/+1
2018-09-05	hw/riscv/virtio: Set the soc device tree node as a simple-bus	Alistair Francis	1	-1/+1
2018-09-04	RISC-V: Use atomic_cmpxchg to update PLIC bitmaps	Michael Clark	1	-27/+22
2018-07-19	spike: Fix crash when introspecting the device	Alistair Francis	1	-6/+4
2018-07-19	riscv_hart: Fix crash when introspecting the device	Alistair Francis	1	-4/+3
2018-07-19	virt: Fix crash when introspecting the device	Alistair Francis	1	-3/+2
2018-07-19	sifive_u: Fix crash when introspecting the device	Alistair Francis	1	-8/+7
2018-07-19	sifive_e: Fix crash when introspecting the device	Alistair Francis	1	-6/+6
2018-07-05	hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device	Alistair Francis	1	-0/+50
2018-07-05	hw/riscv/sifive_u: Move the uart device tree node under /soc/	Alistair Francis	1	-1/+1
2018-07-05	hw/riscv/sifive_u: Set the interrupt controller number of interrupts	Alistair Francis	1	-1/+1
2018-07-05	hw/riscv/sifive_u: Set the soc device tree node as a simple-bus	Alistair Francis	1	-1/+1
2018-07-05	hw/riscv/sifive_plic: Use gpios instead of irqs	Alistair Francis	4	-11/+9
2018-07-05	hw/riscv/sifive_e: Create a SiFive E SoC object	Alistair Francis	1	-25/+69
2018-07-05	hw/riscv/sifive_u: Create a SiFive U SoC object	Alistair Francis	1	-22/+65
2018-07-02	hw/riscv: Use the IEC binary prefix definitions	Philippe Mathieu-Daudé	1	-1/+2
2018-06-01	hw: Do not include "exec/address-spaces.h" if it is not necessary	Philippe Mathieu-Daudé	1	-1/+0
2018-05-10	Merge remote-tracking branch 'remotes/riscv/tags/riscv-qemu-2.13-minor-fixes-...	Peter Maydell	1	-4/+8
2018-05-09	riscv: htif: increase the priority of the htif subregion	KONRAD Frederic	1	-2/+3
2018-05-09	riscv: spike: allow base == 0	KONRAD Frederic	1	-2/+5
2018-05-06	RISC-V: Mark ROM read-only after copying in code	Michael Clark	4	-82/+101
2018-05-06	RISC-V: Remove EM_RISCV ELF_MACHINE indirection	Michael Clark	4	-4/+4
2018-05-06	RISC-V: Remove unused class definitions	Michael Clark	5	-101/+0
2018-05-06	RISC-V: Remove identity_translate from load_elf	Michael Clark	4	-24/+4
2018-05-06	RISC-V: Use ROM base address and size from memmap	Michael Clark	1	-2/+2
2018-05-06	RISC-V: Make virt board description match spike	Michael Clark	1	-1/+1
2018-05-06	RISC-V: Replace hardcoded constants with enum values	Michael Clark	4	-12/+15
2018-04-26	Change references to serial_hds[] to serial_hd()	Peter Maydell	4	-7/+7
2018-03-07	RISC-V Build Infrastructure	Michael Clark	1	-0/+11
2018-03-07	SiFive Freedom U Series RISC-V Machine	Michael Clark	1	-0/+339
2018-03-07	SiFive Freedom E Series RISC-V Machine	Michael Clark	1	-0/+234
2018-03-07	SiFive RISC-V PRCI Block	Michael Clark	1	-0/+89
2018-03-07	SiFive RISC-V UART Device	Michael Clark	1	-0/+176
2018-03-07	RISC-V VirtIO Machine	Michael Clark	1	-0/+420
2018-03-07	SiFive RISC-V Test Finisher	Michael Clark	1	-0/+93