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path: root/hw/riscv/sifive_e.c
AgeCommit message (Expand)AuthorFilesLines
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis1-1/+1
2021-08-26arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell1-1/+0
2021-05-11hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]Bin Meng1-1/+1
2021-05-02Do not include exec/address-spaces.h if it's not really necessaryThomas Huth1-1/+0
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth1-1/+0
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng1-6/+3
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis1-1/+2
2020-09-22sifive_e: Register "revb" as class propertyEduardo Habkost1-5/+6
2020-09-18sifive_e: Rename memmap enum constantsEduardo Habkost1-41/+41
2020-09-09hw/riscv: Move sifive_uart model to hw/charBin Meng1-1/+1
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng1-1/+1
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng1-1/+1
2020-09-09hw/riscv: Move sifive_e_prci model to hw/miscBin Meng1-1/+1
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng1-1/+2
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng1-0/+1
2020-08-25hw/riscv: Allow creating multiple instances of PLICAnup Patel1-1/+1
2020-08-25hw/riscv: Allow creating multiple instances of CLINTAnup Patel1-1/+1
2020-07-22hw/riscv: sifive_e: Correct debug block sizeBin Meng1-1/+1
2020-07-10error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster1-4/+1
2020-07-10qom: Put name parameter before value / visitor parameterMarkus Armbruster1-2/+2
2020-07-10qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster1-2/+1
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng1-4/+6
2020-06-19hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng1-12/+12
2020-06-19sifive_e: Support the revB machineAlistair Francis1-4/+30
2020-06-15qdev: Convert bus-less devices to qdev_realize() with CoccinelleMarkus Armbruster1-2/+1
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2Markus Armbruster1-8/+5
2020-06-15qom: Less verbose object_initialize_child()Markus Armbruster1-3/+1
2020-06-15riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster1-3/+2
2020-06-03riscv: sifive_e: Manually define the machineAlistair Francis1-11/+30
2020-04-29riscv: sifive_e: Support changing CPU typeCorey Wharton1-2/+3
2020-03-17hw/riscv: Let devices own the MemoryRegion they createPhilippe Mathieu-Daudé1-3/+3
2020-03-17hw/riscv: Use memory_region_init_rom() with read-only regionsPhilippe Mathieu-Daudé1-3/+2
2020-02-27hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel1-1/+1
2019-11-25hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)1-1/+1
2019-09-17riscv: sifive_e: Drop sifive_mmio_emulate()Bin Meng1-15/+8
2019-09-17riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}Bin Meng1-2/+2
2019-08-16Include sysemu/sysemu.h a lot lessMarkus Armbruster1-0/+1
2019-08-16Include hw/hw.h exactly where neededMarkus Armbruster1-1/+0
2019-07-05hw/riscv: Replace global smp variables with machine smp propertiesLike Xu1-2/+4
2019-06-27hw/riscv: Split out the boot functionsAlistair Francis1-15/+2
2019-06-23RISC-V: Fix a memory leak when realizing a sifive_ePalmer Dabbelt1-7/+6
2019-05-24SiFive RISC-V GPIO DeviceFabien Chouteau1-2/+26
2019-02-11riscv: Ensure the kernel start address is correctly castAlistair Francis1-1/+1
2019-02-05elf: Add optional function ptr to load_elf() to parse ELF notesLiam Merwick1-1/+1
2018-12-20RISC-V: Enable second UART on sifive_e and sifive_uMichael Clark1-3/+2
2018-09-24Drop "qemu:" prefix from error_report() argumentsMao Zhongyi1-1/+1
2018-07-19sifive_e: Fix crash when introspecting the deviceAlistair Francis1-6/+6
2018-07-05hw/riscv/sifive_plic: Use gpios instead of irqsAlistair Francis1-2/+3
2018-07-05hw/riscv/sifive_e: Create a SiFive E SoC objectAlistair Francis1-25/+69
2018-05-06RISC-V: Mark ROM read-only after copying in codeMichael Clark1-12/+8
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