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| author | Bin Meng <bin.meng@windriver.com> | 2020-06-15 17:50:38 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-06-19 08:25:27 -0700 |
| commit | 495134b75cca3e6a34d4233113c5143439061771 (patch) | |
| tree | 48a0fbb22149134b29b7a7345c4a3a63b169accf /hw/riscv/sifive_e.c | |
| parent | e8905c6ce86f5023f6814abd7c72a809e5d018ec (diff) | |
| download | qemu-495134b75cca3e6a34d4233113c5143439061771.zip qemu-495134b75cca3e6a34d4233113c5143439061771.tar.gz qemu-495134b75cca3e6a34d4233113c5143439061771.tar.bz2 | |
hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
Per the SiFive manual, all E/U series CPU cores' reset vector is
at 0x1004. Update our codes to match the hardware.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-3-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/sifive_e.c')
| -rw-r--r-- | hw/riscv/sifive_e.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 0162682..0cb66ac 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -95,14 +95,16 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DTIM].base, main_mem); /* Mask ROM reset vector */ - uint32_t reset_vec[2]; + uint32_t reset_vec[4]; if (s->revb) { - reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */ + reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */ } else { - reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */ + reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */ } - reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */ + reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */ + + reset_vec[0] = reset_vec[3] = 0; /* copy in the reset vector in little_endian byte order */ for (i = 0; i < sizeof(reset_vec) >> 2; i++) { |