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| author | Alistair Francis <alistair.francis@wdc.com> | 2021-08-30 15:35:15 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-09-21 07:56:49 +1000 |
| commit | 57a3a6226529e60ef4eb5e11b577f2e532a72acc (patch) | |
| tree | 26b5f8a9f08a1ea63b22635e2a0c44e0414293f4 /hw/riscv/sifive_e.c | |
| parent | f436ecc3156dea7edce97e7c247e3667203f5c8b (diff) | |
| download | qemu-57a3a6226529e60ef4eb5e11b577f2e532a72acc.zip qemu-57a3a6226529e60ef4eb5e11b577f2e532a72acc.tar.gz qemu-57a3a6226529e60ef4eb5e11b577f2e532a72acc.tar.bz2 | |
hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer MIP bits.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/riscv/sifive_e.c')
0 files changed, 0 insertions, 0 deletions