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AgeCommit message (Expand)AuthorFilesLines
2025-07-21ppc/xive: Add more interrupt notification tracingGlenn Miles1-0/+6
2025-07-21ppc/xive: Fix xive trace event outputNicholas Piggin1-3/+3
2025-05-14hw/intc/loongarch_pch: Use unified trace event for memory region opsBibo Mao1-6/+2
2025-03-11ppc/xive2: Add support for MMIO operations on the NVPG/NVC BARFrederic Barrat1-0/+4
2025-03-11ppc/xive2: Add grouping level to notificationFrederic Barrat1-1/+1
2025-03-09hw/intc/aspeed: Add Support for Multi-Output IRQ HandlingJamin Lin1-0/+1
2025-03-09hw/intc/aspeed: Refactor INTC to support separate input and output pin indicesJamin Lin1-6/+6
2025-03-09hw/intc/aspeed: Add object type name to trace events for better debuggingJamin Lin1-12/+12
2024-06-16aspeed/intc: Add AST2700 supportJamin Lin1-0/+13
2024-05-09hw/intc/loongarch_ipi: Rename as loongson_ipiJiaxun Yang1-3/+3
2024-05-09hw/intc/loongarch_ipi: Remove pointless MAX_CPU checkJiaxun Yang1-2/+0
2024-04-25hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()Peter Maydell1-0/+1
2024-04-25hw/intc/arm_gicv3: Add NMI handling CPU interface registersPeter Maydell1-0/+1
2024-02-14i386/tcg: implement x2APIC registers MSR accessBui Quang Minh1-2/+2
2023-07-07pnv/xive: Print CPU target in all TIMA tracesFrederic Barrat1-2/+2
2023-05-15hw/intc: Add NULL pointer check on LoongArch ipi deviceSong Gao1-0/+1
2023-01-13hw/intc: Extract the IRQ counting functions into a separate fileThomas Huth1-4/+5
2022-11-04hw/intc: Convert the memops to with_attrs in LoongArch extioiXiaojuan Yang1-2/+1
2022-06-06hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)Xiaojuan Yang1-0/+6
2022-06-06hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)Xiaojuan Yang1-0/+3
2022-06-06hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)Xiaojuan Yang1-0/+9
2022-06-06hw/loongarch: Add LoongArch ipi interrupt support(IPI)Xiaojuan Yang1-0/+4
2022-04-22hw/intc/arm_gicv3_cpuif: Support vLPIsPeter Maydell1-1/+1
2022-04-22hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update()Peter Maydell1-1/+2
2022-04-22hw/intc/arm_gicv3_its: Implement VINVALLPeter Maydell1-0/+1
2022-04-22hw/intc/arm_gicv3_its: Implement VMOVIPeter Maydell1-0/+1
2022-04-22hw/intc/arm_gicv3_its: Implement INV command properlyPeter Maydell1-1/+2
2022-04-22hw/intc/arm_gicv3_its: Implement VSYNCPeter Maydell1-0/+1
2022-04-22hw/intc/arm_gicv3_its: Implement VMOVPPeter Maydell1-0/+1
2022-04-22hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd()Peter Maydell1-0/+2
2022-04-22hw/intc/arm_gicv3_its: Implement VMAPPPeter Maydell1-0/+2
2022-04-22hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTIPeter Maydell1-0/+2
2022-03-07hw/intc/arm_gicv3_its: Add trace events for table reads and writesPeter Maydell1-0/+9
2022-03-07hw/intc/arm_gicv3_its: Add trace events for commandsPeter Maydell1-0/+12
2022-01-28hw/intc/arm_gicv3_its: Add tracepointsPeter Maydell1-0/+8
2021-10-30hw/sh4: Change debug printfs to tracesBALATON Zoltan1-0/+8
2021-08-27xive: Remove extra '0x' prefix in trace eventsCédric Le Goater1-5/+5
2021-06-02docs: fix references to docs/devel/tracing.rstStefano Garzarella1-1/+1
2021-05-12Drop the deprecated lm32 targetMarkus Armbruster1-9/+0
2021-03-15hw/intc: add goldfish-picLaurent Vivier1-0/+8
2021-02-10ppc/pnv: Add trace events for PCI event notificationCédric Le Goater1-0/+3
2020-12-14xive: Add trace eventsCédric Le Goater1-0/+33
2020-10-20hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlersPhilippe Mathieu-Daudé1-0/+4
2019-10-04xics: Rename misleading ics_simple_*() functionsDavid Gibson1-3/+3
2019-10-04xics: Eliminate 'reject', 'resend' and 'eoi' class hooksDavid Gibson1-2/+2
2019-09-23s390x/kvm: Officially require at least kernel 3.15Thomas Huth1-1/+0
2019-05-17ioapic: allow buggy guests mishandling level-triggered interrupts to make pro...Vitaly Kuznetsov1-0/+1
2019-03-22trace-events: Delete unused trace pointsMarkus Armbruster1-1/+0
2019-03-22trace-events: Shorten file names in commentsMarkus Armbruster1-17/+17
2018-08-20nvic: Expose NMI linePeter Maydell1-0/+1
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