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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-10-17 20:07:30 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-10-20 16:12:00 +0100 |
| commit | b68a92f4cb16115025f41bc59e1b2f182a610370 (patch) | |
| tree | 481d337faceeef50bd192aec345cd862484b1a75 /hw/intc/trace-events | |
| parent | a0c0c9f8b4093bf1564d705d8977b6ba46cd2f5a (diff) | |
| download | qemu-b68a92f4cb16115025f41bc59e1b2f182a610370.zip qemu-b68a92f4cb16115025f41bc59e1b2f182a610370.tar.gz qemu-b68a92f4cb16115025f41bc59e1b2f182a610370.tar.bz2 | |
hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
Add trace events for GPU and CPU IRQs.
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201017180731.1165871-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/trace-events')
| -rw-r--r-- | hw/intc/trace-events | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 527c3f7..22782b3 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -199,3 +199,7 @@ nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg wri heathrow_write(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" %u: 0x%"PRIx64 heathrow_read(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" %u: 0x%"PRIx64 heathrow_set_irq(int num, int level) "set_irq: num=0x%02x level=%d" + +# bcm2835_ic.c +bcm2835_ic_set_gpu_irq(int irq, int level) "GPU irq #%d level %d" +bcm2835_ic_set_cpu_irq(int irq, int level) "CPU irq #%d level %d" |