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authorSong Gao <gaosong@loongson.cn>2023-04-06 15:11:31 +0800
committerSong Gao <gaosong@loongson.cn>2023-05-15 19:09:33 +0800
commit7ef0eb35a4e6961d7e40f03f16ed241c95ae93f9 (patch)
treeddd4866838ad501e49382744c48e5fe6857736e9 /hw/intc/trace-events
parent646c39b220f789158313fee5d207f370e29c586a (diff)
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hw/intc: Add NULL pointer check on LoongArch ipi device
When ipi mailbox is used, cpu_index is decoded from iocsr register. cpu maybe does not exist. This patch adds NULL pointer check on ipi device. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230512100421.1867848-4-gaosong@loongson.cn>
Diffstat (limited to 'hw/intc/trace-events')
-rw-r--r--hw/intc/trace-events1
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 50cadfb..5c6094c 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -292,6 +292,7 @@ sh_intc_set(int id, int enable) "setting interrupt group %d to %d"
# loongarch_ipi.c
loongarch_ipi_read(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
loongarch_ipi_write(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64
+loongarch_ipi_unsupported_cpuid(const char *s, uint32_t cpuid) "%s unsupported cpuid 0x%" PRIx32
# loongarch_pch_pic.c
loongarch_pch_pic_irq_handler(int irq, int level) "irq %d level %d"