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path: root/llvm/test/tools/UpdateTestChecks
AgeCommit message (Expand)AuthorFilesLines
2025-12-09[AArch64] Run optimizeTerminators earlier too. (#170907)David Green2-29/+16
2025-12-08[MCAsmStreamer] Print register names in --show-inst modeAlexander Richardson1-12/+12
2025-12-05[AArch64] Optimize CBZ wzr and friends. (#161508)David Green2-2/+6
2025-11-24[Utils][update_mc_test_checks] Support generating asm tests from templates. (...Ivan Kosarev3-0/+54
2025-11-14AMDGPU: Select vector reg class for divergent build_vector (#168169)Matt Arsenault1-4/+4
2025-11-11AMDGPU: Start using RegClassByHwMode for wavesize operandsMatt Arsenault1-2/+2
2025-11-06Reapply "[utils][UpdateLLCTestChecks] Add MIR support to update_llc_test_chec...Valery Pykhtin6-0/+108
2025-11-05Revert "[utils][UpdateLLCTestChecks] Add MIR support to update_llc_test_check...Valery Pykhtin6-107/+0
2025-11-05[utils][UpdateLLCTestChecks] Add MIR support to update_llc_test_checks.py. (#...Valery Pykhtin6-0/+107
2025-11-01[UTC] CHECK-EMPTY instead of skipping blank lines (#165718)Kunqiu Chen4-12/+113
2025-10-28[UTC] Indent switch cases (#165212)Kunqiu Chen3-0/+163
2025-10-27[UpdateTestChecks][llc] Support `arm64-apple-darwin` (#165092)Tomer Shafir2-18/+0
2025-10-13AMDGPU: Use ELF mangling in data layout (#163011)Matt Arsenault2-8/+8
2025-10-04AMDGPU: Remove LDS_DIRECT_CLASS register class (#161762)Matt Arsenault1-2/+2
2025-10-04AMDGPU: Remove m0 classes (#161758)Matt Arsenault1-2/+2
2025-09-23[UpdateTestChecks] Don't fail silently when conflicting CHECK lines means no ...Alex Bradbury7-1/+124
2025-09-16[AMDGPU] Add aperture classes to VS_64 (#158823)Stanislav Mekhanoshin1-2/+2
2025-09-16[AMDGPU] Drop high 32 bits of aperture registers (#158725)Stanislav Mekhanoshin1-2/+2
2025-09-10[UTC] Record TBAA semantics when autogenerating check linesAntonio Frighetto2-22/+22
2025-09-10[UTC] Introduce test for PR147670 (NFC)Antonio Frighetto3-0/+247
2025-09-03[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)Stanislav Mekhanoshin1-2/+2
2025-09-02AMDGPU: Add VS_64_Align2 class (#156132)Matt Arsenault1-2/+2
2025-08-22[LoopDist] Add metadata for checking post process state of distribute… (#15...Michael Berg1-3/+3
2025-08-19[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)Alex MacLean1-8/+7
2025-08-12[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#1...Philip Reames2-4/+4
2025-08-12[utils][UpdateTestChecks] Warn about possible target triple mismatch (#149645)Tomer Shafir2-0/+18
2025-08-08[IR] Remove size argument from lifetime intrinsics (#150248)Nikita Popov6-56/+56
2025-08-01[llvm] Remove uses of %T in tests (#151621)Aiden Grossman1-3/+4
2025-07-28[NVPTX] Fix v2i8 call lowering, use generic ld/st nodes for call params (#146...Alex MacLean1-6/+6
2025-07-22Fix Windows EH IP2State tables (remove +1 bias) (#144745)sivadeilra1-3/+3
2025-06-27[NVPTX] Fixup v2i8 parameter and return lowering (#145585)Alex MacLean1-1/+1
2025-06-25[NVPTX] Consolidate and cleanup various NVPTXISD nodes (NFC) (#145581)Alex MacLean1-5/+1
2025-05-28[tools] Allow RegClass/Bank in update_givaluetracking_test_checks.py (#141727)Pierre van Houtryve2-3/+3
2025-05-22[GlobalISel] Add a update_givaluetracking_test_checks.py script (#140296)David Green5-0/+67
2025-05-21[LAA] Tweak debug output for UTC stability (#140764)Ramkumar Ramachandra6-25/+190
2025-05-20[LoongArch] Introduce `32s` target feature for LA32S ISA extensions (#139695)hev2-6/+6
2025-05-20update_mir_test_checks: keep comment embedded in MIR (#140016)Ruiling, Song2-0/+2
2025-05-10[NVPTX] use untyped loads and stores where ever possible (#137698)Alex MacLean1-11/+11
2025-05-09update_test_checks: indent dbg records (#139230)Orlando Cazalet-Hyams5-25/+25
2025-04-24update_test_checks: Relax DIFile filename checks (#135692)Scott Linder5-2/+87
2025-04-22Reapply "[AMDGPU] Insert readfirstlane in the function returns in sgpr." (#13...Pankaj Dwivedi1-30/+30
2025-04-21[NVPTX] Improve kernel byval parameter lowering (#136008)Alex MacLean1-6/+6
2025-04-21Revert "[AMDGPU] Insert readfirstlane in the function returns in sgpr. (#1353...Shilei Tian1-30/+30
2025-04-21[AMDGPU] Insert readfirstlane in the function returns in sgpr. (#135326)Pankaj Dwivedi1-30/+30
2025-04-01[DebugInfo][RemoveDIs] Remove debug-intrinsic printing cmdline options (#131855)Jeremy Morse13-1565/+6
2025-03-21[hexagon] Bump the default version to v68 (#132304)Alexey Karyakin2-26/+24
2025-03-18update_test_checks: add new --filter-out-after option (#129739)David Sherwood8-0/+226
2025-03-06[win] NFC: Rename `EHCatchret` to `EHCont` to allow for EH Continuation targe...Daniel Paoliello2-2/+2
2025-02-28[NVPTX] Improve device function byval parameter lowering (#129188)Alex MacLean1-20/+12
2025-02-21[NVPTX][InferAS] assume alloca instructions are in local AS (#121710)Alex MacLean1-6/+6
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