aboutsummaryrefslogtreecommitdiff
path: root/llvm/test/CodeGen/Thumb2
AgeCommit message (Expand)AuthorFilesLines
3 daysIR: Promote "denormal-fp-math" to a first class attribute (#174293)Matt Arsenault3-3/+3
2026-01-21IR: Remove llvm.convert.to.fp16 and llvm.convert.from.fp16 intrinsics (#174484)Matt Arsenault2-42/+0
2026-01-13[SDAG] (setcc (sub nsw a, b), zero, s??) -> (setcc a, b, s??) (#175459)DaKnig1-74/+86
2025-12-14[ARM] Introduce intrinsics for MVE fp-converts under strict-fp. (#170686)David Green1-0/+81
2025-12-14[ARM] Introduce intrinsics for MVE vcmp under strict-fp. (#169798)David Green1-0/+820
2025-12-14[ARM] Introduce intrinsics for MVE vrnd under strict-fp. (#169797)David Green1-0/+123
2025-12-14[ARM][AArch64] Replace ".f16(bfloat" with ".bf16(bfloat" in intrinsics. NFCDavid Green1-66/+34
2025-12-08[DAG] Generate UMULH/SMULH with wider vector types (#170283)David Green1-237/+62
2025-12-02[ARM] Introduce intrinsics for MVE minnm/maxnm under strict-fp. (#169795)David Green1-1/+90
2025-12-02[LSR] Insert the transformed IV increment in the user block (#169515)John Brawn1-6/+3
2025-12-02[ARM] Add tests for over-sized mulh. NFCDavid Green1-30/+463
2025-11-30[ARM] Introduce intrinsics for MVE fma under strict-fp. (#169771)David Green1-12/+112
2025-11-27[ARM] Remove IR from mve vpt mir tests. NFCDavid Green10-230/+23
2025-11-25[ARM] Introduce intrinsics for MVE add/sub/mul under strict-fp. (#169156)David Green3-8/+151
2025-11-24Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16...hstk30-hw6-186/+194
2025-11-23Revert "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16...Aiden Grossman6-194/+186
2025-11-23[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)hstk30-hw6-186/+194
2025-11-21[ARM] Restore hasSideEffects flag on t2WhileLoopSetup (#168948)Sergei Barannikov1-0/+45
2025-11-12DAG: Use poison when widening build_vector (#167631)Matt Arsenault1-1/+1
2025-11-10ARM: Enable terminal rule (#165958)Matt Arsenault13-309/+301
2025-11-06Reland: CodeGen: Record MMOs in finalizeBundle (#166689)Nicolai Hähnle1-22/+23
2025-11-05Revert "CodeGen: Record MMOs in finalizeBundle" (#166520)Jan Patrick Lehr1-23/+22
2025-11-05CodeGen: Record MMOs in finalizeBundle (#166210)Nicolai Hähnle1-22/+23
2025-10-30[LSR] Don't count conditional loads/store as enabling pre/post-index (#159573)John Brawn1-33/+37
2025-10-23[test][ARM] Remove unsafe-fp-math-uses (NFC) (#164744)paperchalice16-16/+16
2025-10-22[ARM][MVE] Invalid tail predication in LowOverheadLoop pass (#163941)Simon Tatham1-0/+146
2025-10-22[ARM][AArch64] BTI,GCS,PAC Module flag update. (#86212)Daniel Kiss1-1/+1
2025-10-20[IR] Replace alignment argument with attribute on masked intrinsics (#163802)Nikita Popov7-92/+92
2025-10-15[LowOverheadLoops] Generate test checks (NFC)Nikita Popov4-138/+760
2025-10-13[Thumb2] carry.ll - regenerate test checks (#163173)Simon Pilgrim1-21/+38
2025-10-11Fix legalizing `FNEG` and `FABS` with `TypeSoftPromoteHalf` (#156343)beetrees1-30/+14
2025-10-07[ARM] Add mayRaiseFPException to appropriate instructions and mark all instru...Erik Enikeev10-170/+170
2025-10-04[RegAlloc] Remove default restriction on non-trivial rematerialization (#159211)Luke Lau13-737/+662
2025-10-02PeepholeOpt: Fix losing subregister indexes on full copies (#161310)Matt Arsenault2-299/+156
2025-09-26[ARM] Add extra mulh tests with known-bits. NFCDavid Green1-12/+247
2025-09-26[RegAlloc] Account for use availability when applying rematerializable weight...Luke Lau1-5/+10
2025-09-19[ARM] Replace ABS and tABS machine nodes with custom lowering (#156717)AZero131-19/+40
2025-09-19Greedy: Take copy hints involving subregisters (#159570)Matt Arsenault2-44/+37
2025-09-12[ARM] Make test more robust (NFC)Nikita Popov1-2/+2
2025-09-10Revert "[DAGCombiner] Relax condition for extract_vector_elt combine" (#157953)Arthur Eubanks16-648/+941
2025-09-10[DAGCombiner] Relax condition for extract_vector_elt combine (#157658)ZhaoQi16-941/+648
2025-09-09[clang][driver][arm][macho] Default to -mframe-pointer=non-leaf. (#154216)Francesco Petrogalli1-0/+8
2025-08-31[TargetLowering] Only freeze LHS and RHS if they are used multiple times in e...AZero131-6/+6
2025-08-19[RegAllocFast] Don't align stack slots if the stack can't be realigned (#153682)Craig Topper1-49/+49
2025-08-13[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)Shoreshen15-31/+31
2025-08-12[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#1...Philip Reames97-259/+259
2025-07-21[IR] Only allow lifetime.start/end on allocas (#149310)Nikita Popov1-1/+2
2025-07-15Remove Native Client support (#133661)Brad Smith1-3/+3
2025-07-15[CostModel] Handle all cost kinds in getCmpSelInstrCost (#148233)David Green1-23/+19
2025-07-14[LSR] Account for hardware loop instructions (#147958)John Brawn2-22/+327
generated by cgit v1.1 at 2026-02-09 00:22:47 +0000