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AgeCommit message (Expand)AuthorFilesLines
4 days[NVPTX] Remove `NoSignedZerosFPMath` uses (#180086)paperchalice1-15/+15
5 daysRevert "Reland "[NVPTX] Validate user-specified PTX version against SM versio...Justin Fargnoli13-73/+36
5 daysReland "[NVPTX] Validate user-specified PTX version against SM version" (#179...Justin Fargnoli13-36/+73
5 daysIR: Promote "denormal-fp-math" to a first class attribute (#174293)Matt Arsenault10-11/+11
5 daysReland "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#1...Akshay Deodhar11-957/+9382
6 days[NVPTX][NFC] Update fence.py and cmpxchg.py to generate ptxas-sm_XY and ptxas...Akshay Deodhar7-12/+21
6 days[LowerMemIntrinsics] Optimize memset lowering (#169040)Fabian Ritter1-4/+4
7 days[NVPTX] Print PM Event Mask value as unsigned integer. (#178891)Kirill Vedernikov1-2/+18
13 daysRevert "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#1...Akshay Deodhar11-9382/+957
13 days[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)Akshay Deodhar11-957/+9382
2026-01-26Revert "[NVPTX] Weak cmpxchg unittests for NVPTX" (#178090)Vladimir Vereschaka4-9048/+3694
2026-01-26Revert "Reland "[NVPTX] Validate user-specified PTX version against SM versio...Justin Fargnoli13-73/+36
2026-01-26Reland "[NVPTX] Validate user-specified PTX version against SM version" (#177...Justin Fargnoli13-36/+73
2026-01-22[NVPTX] fix illegal name for .extern .shared global variables (#173018)Kjetil Kjeka1-0/+6
2026-01-22[NVPTX] Weak cmpxchg unittests for NVPTX (#176078)Akshay Deodhar4-3694/+9048
2026-01-22[NVPTX] Update the default SM to 7.5 (#176021)Justin Fargnoli4-8/+18
2026-01-21IR: Remove llvm.convert.to.fp16 and llvm.convert.from.fp16 intrinsics (#174484)Matt Arsenault1-46/+0
2026-01-20[clang][NVPTX] Add missing half-precision add/mul/fma intrinsics (#170079)Srinivasa Ravi4-0/+326
2026-01-19[LLVM][NVPTX] Add support for tcgen05.ld.red Instruction (#175919)Pradeep Kumar1-0/+389
2026-01-18StackProtector: Use LibcallLoweringInfo analysis (#170329)Matt Arsenault1-1/+1
2026-01-13Revert "[NVPTX] Validate user-specified PTX version against SM version" (#175...Mehdi Amini13-73/+36
2026-01-12[NVPTX] Validate user-specified PTX version against SM version (#174834)Justin Fargnoli13-36/+73
2026-01-12 [Clang] Add `__builtin_stack_address` (#148281)moorabbit1-0/+9
2026-01-08[NVPTX] Use correct `mul.wide` operand type when matching on `shl` in `combin...Justin Fargnoli1-0/+35
2026-01-08[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)Pradeep Kumar22-775/+997
2026-01-02[NVPTX] Add missing preconditions to tensormap replace tests (#174190)Srinivasa Ravi2-2/+2
2026-01-01[NVPTX] Add proper precondition in tensormap_replace_sm_103a test (#174144)Walter Lee1-1/+1
2026-01-01[NVPTX] Add intrinsics and codegen for tensormap.replace (#172458)Srinivasa Ravi4-0/+368
2025-12-21[MLIR][NVPTX] Add intrinsics and Ops to read smem-sizes (#173089)Durgadoss R2-0/+46
2025-12-19[NVPTX] Add missing type suffixes for barrier.cta.red (#172945)Alex MacLean1-48/+48
2025-12-18[NVPTX] Add support for barrier.cta.red.* instructions (#172541)Alex MacLean1-0/+174
2025-12-17fix `llvm.fma.f16` double rounding issue when there is no native support (#17...Folkert de Vries2-36/+45
2025-12-17[NVPTX][DagCombiner] Eliminate guards on shift amount because PTX shifts auto...Yonah Goldberg1-0/+379
2025-12-15[clang][NVPTX] Add support for mixed-precision FP arithmetic (#168359)Srinivasa Ravi3-0/+628
2025-12-13[SelectionDAG] Support integer types with multiple registers in ComputePHILiv...Craig Topper1-212/+208
2025-12-12[NVPTX] Fixup and refactor brx.idx support (#171933)Alex MacLean2-86/+194
2025-12-09[NVPTX] Add IR pass for FMA transformation in the llc pipeline (#154735)Rajat Bajpai1-0/+247
2025-12-08[NVPTX] Fix lit test issue from used_bytes_mask (#171220)Drew Kersnar3-3/+38
2025-12-08[LoadStoreVectorizer] Fill gaps in load/store chains to enable vectorization ...Drew Kersnar3-23/+110
2025-12-03[MachineBasicBlock] Don't split loop header successor if the terminator is un...Hongyu Chen2-0/+255
2025-12-03[Support] Support debug counters in non-assertion builds (#170468)Nikita Popov1-5/+0
2025-12-03[LowerMemIntrinsics] Factor control flow generation out of the memcpy lowerin...Fabian Ritter1-14/+14
2025-11-25[NVPTX] Fix lit test issues from masked load/store implementation (#169535)Drew Kersnar3-7/+7
2025-11-25[NVPTX] Lower LLVM masked vector loads and stores to PTX (#159387)Drew Kersnar6-18/+754
2025-11-24[NVPTX] Use PRMT instruction to lower i16 bswap (#168968)Chengjun1-41/+33
2025-11-24Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16...hstk30-hw4-121/+121
2025-11-23Revert "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16...Aiden Grossman4-121/+121
2025-11-23[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)hstk30-hw4-121/+121
2025-11-21[NVPTX] Support for dense and sparse MMA intrinsics with block scaling. (#163...Kirill Vedernikov2-2/+346
2025-11-20Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#...Matt Arsenault7-124/+128
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