aboutsummaryrefslogtreecommitdiff
path: root/llvm/test/CodeGen/MIR
AgeCommit message (Expand)AuthorFilesLines
21 hours[RISCV] Print MIR comments for AVL and VEC_RM operands (#179542)Min-Yih Hsu1-1/+1
4 days[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)vporpo2-0/+138
6 days[AMDGPU] Remove `NoSignedZerosFPMath` uses (#178343)paperchalice6-14/+0
6 days[AArch64] Use GISel for optnone functions (#174746)Ryan Cowan1-2/+2
9 days[AMDGPU] Improve crash message when S_WAITCNT_DEPCTR is missing its operand (...vporpo1-0/+9
2026-01-13[MIR] Add parsing for ehscope_entry. (#175592)David Green1-0/+16
2025-12-22[AMDGPU] Fix mir-canon-multi-def.mir test (#173243)Frederik Harwath1-4/+3
2025-12-22[MIRVRegNamerUtils] Handle instructions with multiple definitions (#172982)Frederik Harwath1-0/+23
2025-12-03[CodeGen] Add MO_LaneMask type and a new COPY_LANEMASK instruction (#151944)Vikash Gupta5-0/+69
2025-11-26Add IR and codegen support for deactivation symbols.Peter Collingbourne1-0/+12
2025-11-25[NVPTX] Lower LLVM masked vector loads and stores to PTX (#159387)Drew Kersnar1-4/+4
2025-11-22[AMDGPU] Enable serializing of allocated preload kernarg SGPRs info (#168374)tyb080710-0/+322
2025-10-24[GlobalISel] Make scalar G_SHUFFLE_VECTOR illegal. (#140508)David Green2-51/+15
2025-10-13[NFC][MIR] Fix extra whitespace in MIR printing (#162928)Rahul Joshi1-1/+1
2025-09-23[MIR][NFC] Build fix after 1132e82 (#160273)Elizaveta Noskova1-0/+2
2025-09-23[MIR] Support save/restore points with independent sets of registers (#119358)Elizaveta Noskova2-0/+158
2025-09-16[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)Shilei Tian4-4/+4
2025-09-11[AArch64][MIR] Serialize AArch64MachineFunctionInfo::HasStackFrame to MIR (#1...David Tellenbach1-0/+41
2025-09-03[AMDGPU] Remove most uses of /dev/null in tests (#156630)Jay Foad28-28/+28
2025-08-12[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#1...Philip Reames9-28/+28
2025-08-12[llvm] Support multiple save/restore points in mir (#119357)Elizaveta Noskova3-4/+87
2025-08-08[AMDGPU] AsmPrinter: Unify arg handling (#151672)Diana Picus6-0/+26
2025-07-30[llvm] Extract and propagate callee_type metadataPrabhu Rajasekaran1-0/+91
2025-07-29[AMDGPU] Add NoaliasAddrSpace to AAMDnodes (#149247)Shoreshen3-0/+93
2025-07-28Reapply "[llvm] Add CalleeTypeIds field to CallSiteInfo" (#150335) (#150990)Prabhu Rajasekaran3-0/+113
2025-07-23Revert "[llvm] Add CalleeTypeIds field to CallSiteInfo" (#150335)Haowei3-113/+0
2025-07-23[llvm] Add CalleeTypeIds field to CallSiteInfoPrabhu Rajasekaran3-0/+113
2025-07-21[AMDGPU] ISel & PEI for whole wave functions (#145858)Diana Picus6-0/+13
2025-07-15[AMDGPU] gfx1250 64-bit relocations and fixups (#148951)Stanislav Mekhanoshin1-3/+13
2025-07-09[NVPTX] Rework and cleanup FTZ ISel (#146410)Alex MacLean1-4/+4
2025-06-27[NVPTX] Fixup v2i8 parameter and return lowering (#145585)Alex MacLean1-2/+2
2025-06-24[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)Diana Picus6-0/+13
2025-06-23[NVPTX] Rename register classes after float register removal (NFC) (#145255)Alex MacLean3-24/+24
2025-06-06[MIRParser] Report register class errors in a deterministic order (#142928)Jay Foad1-4/+3
2025-05-29[NVPTX] Cleanup ISel code after float register removal, use BasicNVPTXInst (#...Alex MacLean3-8/+8
2025-05-21[NVPTX] Remove Float register classes (#140487)Alex MacLean3-22/+22
2025-05-13[NVPTX] Vectorize and lower 256-bit global loads/stores for sm_100+/ptx88+ (#...Drew Kersnar1-4/+4
2025-05-08[CodeGen] Parse nusw flag (#138856)Pierre van Houtryve1-0/+23
2025-05-06[AArch64] Correct position of CFI Instruction for Pointer Authentication (#13...Daniel Kiss1-2/+2
2025-04-15[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)Jun Wang2-2/+2
2025-04-04[Verifier] Require that dbg.declare variable is a ptr (#134355)Nikita Popov1-1/+1
2025-03-27[YAML] fix output incorrect format for block scalar string (#132897)Congcong Cai1-1/+0
2025-03-19[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)Diana Picus6-0/+13
2025-03-17AMDGPU: Migrate more tests away from undef (#131314)Matt Arsenault5-15/+15
2025-03-15MIR: Replace undef with poison in some MIR tests (#131282)Matt Arsenault8-30/+30
2025-03-13[CodeGen][NPM] Port BranchFolder to NPM (#128858)Akshat Oke1-0/+1
2025-03-08[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)Shilei Tian1-2/+1
2025-03-06[win] NFC: Rename `EHCatchret` to `EHCont` to allow for EH Continuation targe...Daniel Paoliello3-12/+12
2025-03-03[win] Enable test/CodeGen/MIR/AArch64 on Windows (#122832)Daniel Paoliello1-4/+0
2025-03-03[RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (#120557)Akshat Oke1-0/+1
generated by cgit v1.1 at 2026-02-04 19:28:21 +0000